News


ChipNation 2024 IMSE
CHIPNATION 2024: IMSE explores opportunities and challenges of neuromorphic technology

IMSE Full Professor of Research Bernabé Linares-Barranco participated as panelist in CHIPNATION 2024, the congress on microelectronics organized by "Asociación Española de la Industria de Semiconductores" – AESEMI, on 2-3 of December 2024 in Valencia.
December 12, 2024

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Buscanidos App IMSE
Buscanidos: play and contribute to the conservation of the Kentish Plover

Since October, the Museo Casa de la Ciencia in Seville has hosted the innovative interactive application Buscanidos, developed by Gustavo Liñán-Cembrano, a researcher at the Instituto de Microelectrónica de Sevilla (IMSE-CNM).
December 4, 2024

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MathWorks drives advanced modeling and design at IMSE
MathWorks drives advanced modeling and design at IMSE

Technicians from MathWorks, a U.S.-based corporation specializing in mathematical computing software, visited IMSE to deliver theoretical and practical workshops on MATLAB.
December 2, 2024

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IMSE participation at European Commission's Science Fair
The IMSE will participate for the second consecutive year in the European Commission's Science Fair

"Science is Wonderful!", the international science fair organized by the European Commission, will take place in Brussels on March 12, 13, and 14, 2025. For the second consecutive year, the event will feature a team of researchers from the Instituto de Microelectrónica de Sevilla (IMSE-CNM).
November 12, 2024

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IMEC visits IMSE
IMEC visits IMSE to explore collaboration opportunities after its arrival in Spain

The visit consisted of a first round of presentations of the different entities and a subsequent tour of the centre's laboratories.
October 28, 2024

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IMSE Publication future PUFs
Resistant to temperature changes: this will be the future of PUFs

From the Instituto de Microelectrónica de Sevilla (IMSE-CNM) we are pleased to announce the recent publication by the journal IEEE Transactions on Circuits and Systems I: Regular Papers of the article entitled "A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs" to which researchers from our center have contributed.
October 8, 2024

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PREVIOUS EVENTS & NEWS

New Director of the IMSE-CNM


IMSE researcher Teresa Serrano Gotarredona has been appointed as the new Director of the Instituto de Microelectrónica de Sevilla.

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Education at IMSE


- Doctoral Studies
- Master Studies
- Degree Studies
- Final Degree Projects
- Internships

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Recent publications


Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract      doi      

This paper presents the design and implementation of a Karatsuba multiplier to accelerate digital signature schemes on embedded systems. The Karatsuba algorithm is integrated into hardware accelerators for RSA and EdDSA, representing a fundamental component of contemporary, state-of-the-art implementations. A hardware/software co-design methodology is employed, implementing the architectures on a System-onChip platform that combines programmable logic with an ARM processor. The results showcase enhanced resource consumption and timing performance for both signature generation and verification, confirming the superiority of EdDSA over RSA when utilizing the same Karatsuba multiplier core and coding techniques.

VLSI integration of a RO-based PUF into a 65 nm technology
P. Ortega-Castro, L.F. Rojas-Muñoz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract      doi      

Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO oscillating frequencies and generate unique identifiers (ID). Its structure makes it suitable for, both, FPGA and ASIC applications. This paper presents a RO-PUF implementation using a semi-custom design methodology in TSMC 65 nm technology which has been validated through the entire design process, manufactured and experimentally characterized. Results show a good performance and robustness against temperature and voltage variations while obtaining up to three bits from each execution to generate digital IDs.

A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs
F. de los Santos-Prieto, F.J. Rubio-Barbero, R. Castro-López, E. Roca and F.V. Fernández
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers (Early Access), 2024
IEEE    ISSN: 1549-8328
abstract      doi      

Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.

A Review of Ising Machines Implemented in Conventional and Emerging Technologies
T. Zhang, Q. Tao, B. Liu, A. Grimaldi, E. Raimondo, M. Jiménez, M.J. Avedillo, J. Núñez, B. Linares-Barranco, T. Serrano-Gotarredona, G. Finocchio and Jie Han
Journal Paper · IEEE Transactions on Nanotechnology (Early Access), 2024
IEEE    ISSN: 1536-125X
abstract      doi      

Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and pase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOSspintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.

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What we do


Our main area of specialization is the design of CMOS analog and mixed-signal integrated circuits and their use in different application contexts such as wireless communications, data conversion, smart imagers & vision sensors, biomedical devices, cybersecurity, neuromorphic computing and space technologies.

The IMSE-CNM staff consists of approximately one hundred people, including scientists and support personnel. IMSE-CNM employees are involved in advancing scientific knowledge, designing high level scientific-technical solutions and in technology transfer.

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