IMSE-CNM

The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4 configurable logic blocks (CLBs) to accommodate the RO bank.

In alignment with the ethos of openness and democracy inherent in the RISC-V architecture, our research endeavors have been directed towards the utilization of open-source tools for the implementation of a simple but didactic RISC-V processor denoted as ASTIRV32I. The paper discusses the design strategies, memory mapping, physical verification procedures, and performance evaluation of the ASTIRV32I processor. Furthermore, it highlights the successful validation of the implemented design through the execution of fundamental algorithms, exemplifying the practicality and viability of the RISC-V-based processor design and serving as a proof-of-concept for open-source FPGA design.

In this demonstrator, a design flow based on a set of open-source tools is showcased, enabling the simulation, synthesis, implementation, and programming of digital systems on programmable logic devices. Three academic examples, increasing in complexity, are shown running on open hardware development boards to demonstrate the validity of the digital design flow based on the APIO environment.

This work proposes the use of open-source Electronic Design Automation (EDA) tools as a didactic instrument in undergraduate and master courses dealing with the design of analog, mixed-signal and digital Integrated Circuits (ICs). The aim is to make it easier for students to get familiar with the whole IC design flow within a real-word application framework, without being limited by licenses or financial barriers imposed by commercial proprietary Computer-Aided Design (CAD) tools. An overview of main tools, design environments and technology processes is given based on the exploratory study carried out within the framework of two master theses. These tools can be easily installed and employed by students to design and verify analog, mixed-signal and digital circuits and Systems-on-Chip (SoC) prototypes. As a case study, a RISC-V processor architecture has been synthesized down to layout level by a master student, to demonstrate the capabilities of these open-source tools to teach and learn microelectronics11This work was supported in part by Grants PID2019-103876RB-I00, PID2021-128009OB-C31, PID2022-138078OB-I00, and PDC2023-145808-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future and by ERDF A way of making Europe..