IMSE-CNM

Implementing innovative concepts in silicon

Research Areas

Analog Signal Processing
Analog Signal Processing

Digital Signal Processing & VLSI Systems
Digital Signal Processing & VLSI Systems

Brain-Inspired Neural Networks and Artificial Intelligence
Brain-Inspired Neural Networks and Artificial Intelligence

Sensory & Photonic Vision Systems
Sensory & Photonic Vision Systems

Nanoelectronics and Emerging Technologies
Nanoelectronics and Emerging Technologies

Biomedical and Bioinspired Circuits and Systems
Biomedical and Bioinspired Circuits and Systems

Integrated Circuits for Space Applications
Integrated Circuits for Space Applications

Hardware Security
Hardware Security

News

Science Fair 2026
IMSE brings technology and innovation to the Science Fair

Once again, the Institute of Microelectronics of Seville has been present at the Science Fair, which is now in its 24th edition.
May 14, 2026

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IMSE European Science 2026
Dodging lasers to understand digital security

Through a laser maze and cryptographic challenges, researchers from the center brought key concepts of digital protection closer to hundreds of students from all over Europe.
March 26, 2026

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IMSE Mathematics Day 2026
Bringing mathematics closer to the classroom to awaken scientific vocations

IMSE researchers bring science outreach to schools to mark International Mathematics Day.
March 16, 2026

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IMSE International Day of Women and Girls in Science 2026
Inspiring the next generation of scientists

At IMSE we carry out several activities to highlight the role of the researchers at our center.
March 2, 2026

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IMSE Science is Wonderful 2026
The IMSE will represent the CSIC at the European Science Fair "Science is Wonderful!" 2026

"Science is Wonderful!", the International Science Fair organized by the European Commission, will be held in Brussels on March 18, 19 and 20, 2026, and will once again feature, for the third consecutive year, the participation of a team of researchers from the Instituto de Microelectrónica de Sevilla (IMSE-CNM).
November 3, 2025

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Award TFM Pablo Navarro IMSE
IMSE signs off on excellence in digital security

The research talent of IMSE shines once again with the "Leonardo Torres Quevedo" Award granted to Pablo Navarro for his Master's Thesis that delves into the security and efficiency of cryptographic algorithms.
October 31, 2025

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PREVIOUS EVENTS & NEWS

New Director of the IMSE-CNM

IMSE researcher Teresa Serrano Gotarredona has been appointed as the new Director of the Instituto de Microelectrónica de Sevilla.

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Education at IMSE

- Doctoral Studies
- Master Studies
- Degree Studies
- Final Degree Projects
- Internships

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Recent publications

Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation
P. Ortega-Castro, E. Camacho-Ruiz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Journal Paper · IEEE Open Journal of the Solid-State Circuits Society (Early Access)
IEEE    ISSN: 2644-1349
abstract      doi      

In increasingly interconnected systems, security has become a critical concern. In this context, delay-based Physical Unclonable Functions (PUFs), such as Ring Oscillator (RO) PUFs, have emerged as key hardware security primitives by providing unique, unpredictable, and reliable responses, addressing security challenges related to key storage and device authentication. To ensure robustness, RO-PUF designs traditionally resort to analog-driven implementation flows, which suffer from high design overhead and limit scalability across technology nodes. We present a configurable RO-PUF design integrated following a standard-cell-based, fully digital semi-custom-design methodology, significantly reducing design effort while enabling portability across planar CMOS technologies. The proposed architecture integrates fully on-chip Helper Data Algorithm (HDA) combined with a lightweight Error Correction Code (ECC) to support key generation, obfuscation, and recovery. Furthermore, it was fabricated in TSMC 65 nm technology and extensively characterized across diverse operating conditions, including process, voltage, and temperature (PVT) variations, achieving state-of-the-art metrics.

Assessment of an FPGA Implementation of a Hybrid PUF Based on a Configurable Transient Effect Ring Oscillator and Ring Oscillator (TERORO-PUF)
A. Casado-Galán, J. Núñez, E. Tena-Sánchez, F.E. Potestad-Ordóñez and A.J. Acosta-Jiménez
Journal Paper · Electronics, vol. 15, no. 3, article 661, 2026
MDPI    ISSN: 2079-9292
abstract      doi      

In the current situation of the Internet of Things (IoT) with its billions of interconnected devices, security in this low-resource environment is paramount. A Physical Unclonable Function (PUF) is a very useful cryptographic primitive which allows us to extract unique information from a particular device in a non-reproducible way. This allows us to use a PUF in cryptography for authentication or secret-key generation. Ring Oscillators (ROs) and Transient Effect Ring Oscillators (TEROs) are oscillating structures used in both FPGAs and ASICs to build PUFs. In this paper we present an FPGA implementation of a PUF based on what we call the ’’TERORO’’ cell (TERO + RO), which is a hybrid structure that allows us to use the different functionalities of both RO and TERO in a single building block. We assess all the possible methods of extracting bits of information from the PUF based on TERORO cells. Finally, we tested the circuit and presented experimental results in terms of its uniqueness, uniformity, and reliability. In RO-counter mode, we obtain 49.74% uniqueness, 54.66% uniformity, and 97.81% reliability across devices, while TERO-based XOR mixing achieves 52.83% uniformity, 45.79% uniqueness, and 93.15% reliability. The FPGA footprint is 142 LUTs, 36 registers, and 82 slices.

Enhancing the performance of HfO2-based memristors with a thin Al2O3 layer: a comparative study
M. Shooshtari, T. Serrano Gotarredona and B. Linares-Barranco
Journal Paper · Journal of Physics D: Applied Physics, vol. 58, no. 45, 2025
IOP Science    
abstract      doi      

The resistive switching behavior of memristors is pivotal for advancing next-generation non-volatile memory and neuromorphic computing devices. In this study, we investigate the impact of incorporating a thin Al2O3 interfacial layer into HfO2-based memristors by fabricating and comparing two device architectures: W/HfO2/Ti/TiN and W/Al2O3/HfO2/Ti/TiN. The Al2O3 layer significantly influences device behavior by altering the electric field distribution and suppressing oxygen vacancy diffusion, leading to more confined and stable filament formation. While the dual-layer structure exhibits higher forming voltages due to increased dlectric thickness and the insulating properties of Al2O3, it also demonstrates improved switching uniformity, reduced resistance variability, and enhanced cycle-to-cycle endurance. Variability, quantified as resistance state variation over repeated cycles, was notably improved in the Al2O3-based device, with resistance fluctuations reduced by nearly 50% compared to the single-layer HfO2 device. These results highlight the role of interfacial engineering in improving memristor stability and reliability, offering valuable design strategies for future memory and neuromorphic computing systems.

A Side-Channel Protected and High-Performance Hardware Implementation for EdDSA25519
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · IEEE Access Vol 13
IEEE    ISSN: 2169-3536
abstract      doi      

This paper presents a high-performance and secure hardware implementation of the Edwards-Curve Digital Signature Algorithm (EdDSA25519). Using the fixed-base signed multi-comb and the k-ary algorithms for scalar multiplication, the proposed design achieves 307%, 253%, and 48% faster performance in key generation, signature generation, and signature verification, respectively, compared to the fastest previous hardware implementation in the state-of-the-art. When compared to the software-based OpenSSL implementation, our design demonstrates timing performance improvements ranging from 1000% to 2200%. Additionally, we integrate robust Side-Channel Attack (SCA) countermeasures and validate their effectiveness through Test Vector Leakage Assessment (TVLA). The results demonstrate increased resistance to Simple Power Analysis (SPA) and Differential Power Analysis (DPA), offering a hardware-based secure solution for modern cryptographic applications.

ALL PUBLICATIONS

IMSE corporate video

What we do

Our main area of specialization is the design of CMOS analog and mixed-signal integrated circuits and their use in different application contexts such as wireless communications, data conversion, smart imagers & vision sensors, biomedical devices, cybersecurity, neuromorphic computing and space technologies.

The IMSE-CNM staff consists of approximately one hundred people, including scientists and support personnel. IMSE-CNM employees are involved in advancing scientific knowledge, designing high level scientific-technical solutions and in technology transfer.

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IMSE-related sites

Master in Microelectronics. Design and Applications of Micro/Nanometrics Systems

Physical Sciences and Technologies Doctoral Programme

Informatics Engineering Doctoral Programme

SIMSIDES: A Time-Domain Behavioral Simulator for Sigma-Delta Modulators in MATLAB/SIMULINK

SHORES: Software & Hardware Open Repository for Embedded Systems

Fuzzy Logic Design Tools

IMSE in the media
IMSE in the media

The World of Chips
The World of Chips

Catalog of Scientific-Technical Services
Catalog of Scientific-Technical Services

Career at IMSE
Career at IMSE