Recent publications
Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management
S. Sánchez-Solano, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 24, no. 17, article 5674, 2024
MDPI ISSN: 1424-8220
abstract
doi
The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4
configurable logic blocks (CLBs) to accommodate the RO bank.
Full Open-Source Implementation of an Academic RISC-V on FPGA
P. Navarro-Torrero, M.C. Martínez-Rodríguez, A. Barriga-Barros and P. Brox
Journal Paper · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
IEEE ISSN: 2766-2616
abstract
doi
In alignment with the ethos of openness and democracy inherent in the RISC-V architecture, our research endeavors have been directed towards the utilization of open-source tools for the implementation of a simple but didactic RISC-V processor denoted as ASTIRV32I. The paper discusses the design strategies, memory mapping, physical verification procedures, and performance evaluation of the ASTIRV32I processor. Furthermore, it highlights the successful validation of the implemented design through the execution of fundamental algorithms, exemplifying the practicality and viability of the RISC-V-based processor design and serving as a proof-of-concept for open-source FPGA design.
Digital Design Flow Based on Open Tools for Programmable Logic Devices
P. Navarro-Torrero, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez, A. Barriga-Barros, C.J. Jiménez-Fernández, M. Brox and P. Brox
Journal Paper · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
IEEE ISSN: 2766-2616
abstract
doi
In this demonstrator, a design flow based on a set of open-source tools is showcased, enabling the simulation, synthesis, implementation, and programming of digital systems on programmable logic devices. Three academic examples, increasing in complexity, are shown running on open hardware development boards to demonstrate the validity of the digital design flow based on the APIO environment.
On the Use of Open-Source EDA Tools for Teaching and Learning Microelectronics
I. Galán-Benítez, R. Carmona-Galán and J.M. de la Rosa
Journal Paper · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
IEEE ISSN: 2766-2616
abstract
doi
This work proposes the use of open-source Electronic Design Automation (EDA) tools as a didactic instrument in undergraduate and master courses dealing with the design of analog, mixed-signal and digital Integrated Circuits (ICs). The aim is to make it easier for students to get familiar with the whole IC design flow within a real-word application framework, without being limited by licenses or financial barriers imposed by commercial proprietary Computer-Aided Design (CAD) tools. An overview of main tools, design environments and technology processes is given based on the exploratory study carried out within the framework of two master theses. These tools can be easily installed and employed by students to design and verify analog, mixed-signal and digital circuits and Systems-on-Chip (SoC) prototypes. As a case study, a RISC-V processor architecture has been synthesized down to layout level by a master student, to demonstrate the capabilities of these open-source tools to teach and learn microelectronics11This work was supported in part by Grants PID2019-103876RB-I00, PID2021-128009OB-C31, PID2022-138078OB-I00, and PDC2023-145808-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future and by ERDF A way of making Europe..
Live Demonstration: Using ANNs to Predict the Evolution of Spectrum Occupancy
G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
IEEE ISSN: 2158-1525
abstract
doi
This demo shows how to use Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum with application in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, different kinds of ANNs - including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them - are trained and tested with experimental datasets taken from measurements of the frequency spectrum. Trained ANNs are embedded in an IoT device based on a Rasperry Pi and connected with a SDR board to detect the activity of Radio-Frequency (RF) signals around the frequency band of 2.4GHz, shared by several wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real time and is able to detect in advance which portions of this frequency band will be less occupied, thus showing their potential application in SDR/CR terminals. ISCAS Track: Analog Signal Processing.
Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks
G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
IEEE ISSN: 2158-1525
abstract
doi
This demo shows how to use Artificial Neural Networks (ANNs) for the optimization and automated design of analog and mixed-signal circuits. A step-by-step procedure is demonstrated to explain the key and practical aspects to consider in this approach, such as dataset preparation, ANNs modeling, training, and optimization of network hyperparameters. Two case studies at different abstraction levels are presented. The first one is the system-level sizing of Sigma-Delta Modulators (ΣΔMs), where ANNs are combined with behavioral simulations to generate valid circuit-level design variables for a given set of specifications. The second example combines ANNs with electrical simulators to optimize the circuit-level design of operational transconductance amplifiers. The methods and tools shown in the demo can be used for the optimization of any arbitrary analog and mixed-signal integrated circuits and systems 1 .ISCAS Track: Analog Signal Processing.
Exploiting randomly distributed pores in photonic structures for security applications to create hardware-based digital identity
D. Martín-Sánchez and P. Brox
Conference · NanoSpain Conf 2024, Tarragona, España
abstract
In the 2024 edition, the conference will strength collaborations with the COST network Netpore in the field of porous semiconductors and oxides. The intersection of nanoSpain2024 and the thematic network COST will encourage collaborative dialogues and the initiation of potential partnerships between researchers and industry professionals. More info at
https://www.nanospainconf.org/2024 A CMOS-compatible oscillation-based VO2 Ising machine solver
O. Maher, M. Jiménez, C. Delacour, N. Harnack, J. Núñez, M.J. Avedillo, B. Linares-Barranco, A. Todri-Sanial, G. Indiveri and S. Karg
Journal Paper · Nature Communications vol. 15, article 3334, 2024
NATURE ISSN: 2041-1723
abstract
doi
Phase-encoded oscillating neural networks offer compelling advantages over metal-oxide-semiconductor-based technology for tackling complex optimization problems, with promising potential for ultralow power consumption and exceptionally rapid computational performance. In this work, we investigate the ability of these networks to solve optimization problems belonging to the nondeterministic polynomial time complexity class using nanoscale vanadium-dioxide-based oscillators integrated onto a Silicon platform. Specifically, we demonstrate how the dynamic behavior of coupled vanadium dioxide devices can effectively solve combinatorial optimization problems, including Graph Coloring, Max-cut, and Max-3SAT problems. The electrical mappings of these problems are derived from the equivalent Ising Hamiltonian formulation to design circuits with up to nine crossbar vanadium dioxide oscillators. Using sub-harmonic injection locking techniques, we binarize the solution space provided by the oscillators and demonstrate that graphs with high connection density (μ > 0.4) converge more easily towards the optimal solution due to the small spectral radius of the problema’s equivalent adjacency matrix. Our findings indicate that these systems achieve stability within 25 oscillation cycles and exhibit power efficiency and potential for scaling that surpasses available commercial options and other technologies under study. These results pave the way for accelerated parallel computing enabled by large-scale networks of interconnected oscillators.
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
M. Srivastava, A. Ferro, A. Sidun, P. Cantillon-Murphy, Daniel O’Hare, K. O’Donoghue and J.M. de la Rosa
Journal Paper · IEEE Open Journal of Circuits and Systems (Volume 5), 2024
IEEE ISSN: 2644-1225
abstract
doi
This work presents a small-area 2nd-order continuous-time ΔΣ Modulator (CTΔΣM) with a single low dropout regulator (LDO) serving as both the power supply for the CTΔΣM and reference voltage buffer. The CTΔΣM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CTΔΣM consumes 300 μW of power when clocked at 10.24 MHz. The CTΔΣM achieves a state-of-the-art area of 0.07 mm.
