Publicaciones recientes
Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
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This paper presents the design and implementation of a Karatsuba multiplier to accelerate digital signature schemes on embedded systems. The Karatsuba algorithm is integrated into hardware accelerators for RSA and EdDSA, representing a fundamental component of contemporary, state-of-the-art implementations. A hardware/software co-design methodology is employed, implementing the architectures on a System-onChip platform that combines programmable logic with an ARM processor. The results showcase enhanced resource consumption and timing performance for both signature generation and verification, confirming the superiority of EdDSA over RSA when utilizing the same Karatsuba multiplier core and coding techniques.
VLSI integration of a RO-based PUF into a 65 nm technology
P. Ortega-Castro, L.F. Rojas-Muñoz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
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Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO oscillating frequencies and generate unique identifiers (ID). Its structure makes it suitable for, both, FPGA and ASIC applications. This paper presents a RO-PUF implementation using a semi-custom design methodology in TSMC 65 nm technology which has been validated through the entire design process, manufactured and experimentally characterized. Results show a good performance and robustness against temperature and voltage variations while obtaining up to three bits from each execution to generate digital IDs.
A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs
F. de los Santos-Prieto, F.J. Rubio-Barbero, R. Castro-López, E. Roca and F.V. Fernández
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers (Early Access), 2024
IEEE ISSN: 1549-8328
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Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.
A Review of Ising Machines Implemented in Conventional and Emerging Technologies
T. Zhang, Q. Tao, B. Liu, A. Grimaldi, E. Raimondo, M. Jiménez, M.J. Avedillo, J. Núñez, B. Linares-Barranco, T. Serrano-Gotarredona, G. Finocchio and Jie Han
Journal Paper · IEEE Transactions on Nanotechnology (Early Access), 2024
IEEE ISSN: 1536-125X
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Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and pase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOSspintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management
S. Sánchez-Solano, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 24, no. 17, article 5674, 2024
MDPI ISSN: 1424-8220
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The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4
configurable logic blocks (CLBs) to accommodate the RO bank.
Full Open-Source Implementation of an Academic RISC-V on FPGA
P. Navarro-Torrero, M.C. Martínez-Rodríguez, A. Barriga-Barros and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
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In alignment with the ethos of openness and democracy inherent in the RISC-V architecture, our research endeavors have been directed towards the utilization of open-source tools for the implementation of a simple but didactic RISC-V processor denoted as ASTIRV32I. The paper discusses the design strategies, memory mapping, physical verification procedures, and performance evaluation of the ASTIRV32I processor. Furthermore, it highlights the successful validation of the implemented design through the execution of fundamental algorithms, exemplifying the practicality and viability of the RISC-V-based processor design and serving as a proof-of-concept for open-source FPGA design.
Digital Design Flow Based on Open Tools for Programmable Logic Devices
P. Navarro-Torrero, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez, A. Barriga-Barros, C.J. Jiménez-Fernández, M. Brox and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
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In this demonstrator, a design flow based on a set of open-source tools is showcased, enabling the simulation, synthesis, implementation, and programming of digital systems on programmable logic devices. Three academic examples, increasing in complexity, are shown running on open hardware development boards to demonstrate the validity of the digital design flow based on the APIO environment.
On the Use of Open-Source EDA Tools for Teaching and Learning Microelectronics
I. Galán-Benítez, R. Carmona-Galán and J.M. de la Rosa
Journal Paper · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
IEEE ISSN: 2766-2616
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This work proposes the use of open-source Electronic Design Automation (EDA) tools as a didactic instrument in undergraduate and master courses dealing with the design of analog, mixed-signal and digital Integrated Circuits (ICs). The aim is to make it easier for students to get familiar with the whole IC design flow within a real-word application framework, without being limited by licenses or financial barriers imposed by commercial proprietary Computer-Aided Design (CAD) tools. An overview of main tools, design environments and technology processes is given based on the exploratory study carried out within the framework of two master theses. These tools can be easily installed and employed by students to design and verify analog, mixed-signal and digital circuits and Systems-on-Chip (SoC) prototypes. As a case study, a RISC-V processor architecture has been synthesized down to layout level by a master student, to demonstrate the capabilities of these open-source tools to teach and learn microelectronics11This work was supported in part by Grants PID2019-103876RB-I00, PID2021-128009OB-C31, PID2022-138078OB-I00, and PDC2023-145808-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future and by ERDF A way of making Europe..
Live Demonstration: Using ANNs to Predict the Evolution of Spectrum Occupancy
G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
IEEE ISSN: 2158-1525
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This demo shows how to use Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum with application in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, different kinds of ANNs - including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them - are trained and tested with experimental datasets taken from measurements of the frequency spectrum. Trained ANNs are embedded in an IoT device based on a Rasperry Pi and connected with a SDR board to detect the activity of Radio-Frequency (RF) signals around the frequency band of 2.4GHz, shared by several wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real time and is able to detect in advance which portions of this frequency band will be less occupied, thus showing their potential application in SDR/CR terminals. ISCAS Track: Analog Signal Processing.
Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks
G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
IEEE ISSN: 2158-1525
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This demo shows how to use Artificial Neural Networks (ANNs) for the optimization and automated design of analog and mixed-signal circuits. A step-by-step procedure is demonstrated to explain the key and practical aspects to consider in this approach, such as dataset preparation, ANNs modeling, training, and optimization of network hyperparameters. Two case studies at different abstraction levels are presented. The first one is the system-level sizing of Sigma-Delta Modulators (ΣΔMs), where ANNs are combined with behavioral simulations to generate valid circuit-level design variables for a given set of specifications. The second example combines ANNs with electrical simulators to optimize the circuit-level design of operational transconductance amplifiers. The methods and tools shown in the demo can be used for the optimization of any arbitrary analog and mixed-signal integrated circuits and systems 1 .ISCAS Track: Analog Signal Processing.
