Encontrados resultados para:
Autor: Ángel Rodríguez Vázquez
Año: Desde 2002
Artículos de revistas
A Low-Latency, Low-Power CMOS Sun Sensor for Attitude Calculation Using Photovoltaic Regime and On-Chip Centroid Computation
R. Gomez-Merchan, J. A. Leñero-Bardallo, M. López-Carmona and Á. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Instrumentation and Measurement, 2023
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The demand for sun sensors has skyrocketed in the last years due to the huge expected deployment of satellites associated with the New Space concept. Sun sensors compute the position of the sun relative to the observer and play a crucial role in navigation systems. However, the sensor itself and the associated electronics must be able to operate in harsh environments. Thus, reducing hardware and post-processing resources improves the robustness of the system. Furthermore, reducing power consumption increases the lifetime of microsatellites with a limited power budget. This work describes the design, implementation, and characterization of a proof-of-concept prototype of a low-power, high-speed sun sensor architecture. The proposed sensor uses photodiodes working in the photovoltaic regime and event-driven vision concepts to overcome the limitations of conventional digital sun sensors in terms of latency, data throughput, and power consumption. The temporal resolution of the prototype is in the microsecond range with an average power consumption lower than 100μW . Experimental results are discussed and compared with the state-of-the-art.
A Pipelining-Based Heterogeneous Scheduling and Energy-Throughput Optimization Scheme for CNNs Leveraging Apache TVM
D. Velasco-Montero, B. Goossens, J. Fernández-Berni, Á. Rodríguez-Vázquez and W. Philips
Journal Paper · IEEE Access, 2023
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Extracting information of interest from continuous video streams is a strongly demanded computer vision task. For the realization of this task at the edge using the current de-facto standard approach, i.e., deep learning, it is critical to optimize key performance metrics such as throughput and energy consumption according to prescribed application requirements. This allows achieving timely decision-making while extending the battery lifetime as much as possible. In this context, we propose a method to boost neural-network performance based on a co-execution strategy that exploits hardware heterogeneity on edge platforms. The enabling tool is Apache TVM, a highly efficient machine-learning compiler compatible with a diversity of hardware back-ends. The proposed approach solves the problem of network partitioning and distributes the workloads to make concurrent use of all the processors available on the board following a pipeline scheme. We conducted experiments on various popular CNNs compiled with TVM on the Jetson TX2 platform. The experimental results based on measurements show a significant improvement in throughput with respect to a single-processor execution, ranging from 14% to 150% over all tested networks. Power-efficient configurations were also identified, accomplishing energy reductions above 10%.
A high-voltage floating level shifter for a multi-stage charge-pump in a standard 1.8 V/3.3 V CMOS process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 156, article 154389, 2022
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This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA.
A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · Sensors, vol. 22, no. 17, article 6429, 2022
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This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm(2). Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode-tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology's nominal supply, (2) residual charge-without passive discharging phase-was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.
An Efficient TDC using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA
M. Parsakordasiabi, I. Vornicu, A. Rodriguez-Vazquez and R. Carmona-Galan
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 71, article 2000413, 2022
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FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mode tapped-delay-line (TDL)-propagating 1's and 0's in alternating measurement cycles-architecture for a field-programmable gate array (FPGA)-based TDC that complies with the mentioned specifications. The dead-time of the proposed TDC is reduced to one system clock cycle by using a toggling input stage and a dual-mode counter-based encoder. To improve the TDC linearity, the TDL sampling sequence is tuned separately for each operating mode. The presented architecture employs a low-resources dual-mode combinatory encoder of one- and zero-counters to remove the bubbles and cover both operating modes. A dual-mode bin-width calibration has been carried out to improve the TDC performance in each mode. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. Experimental results have shown a differential nonlinearity (DNL) within [-0.71 1.05] least significant bit (LSB) and an integral nonlinearity (INL) within [-0.85 0.86] LSB for the propagation of 1's. DNL and INL are within [-0.73 1.06] LSB and [-1.17 0.04] LSB, respectively, for the propagation of 0's. The LSB size is 22.1 ps and the TDC precision is 22.35 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.
Architecture-Level Optimization on Digital Silicon Photomultipliers for Medical Imaging
F. Bandi, V. Ilisie, I. Vornicu, R. Carmona-Galan, J.M. Benlloch and A. Rodriguez-Vazquez
Journal Paper · Sensors, vol. 22, no. 1, article 122, 2022
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Silicon photomultipliers (SiPMs) are arrays of single-photon avalanche diodes (SPADs) connected in parallel. Analog silicon photomultipliers are built in custom technologies optimized for detection efficiency. Digital silicon photomultipliers are built in CMOS technology. Although CMOS SPADs are less sensitive, they can incorporate additional functionality at the sensor plane, which is required in some applications for an accurate detection in terms of energy, timestamp, and spatial location. This additional circuitry comprises active quenching and recharge circuits, pulse combining and counting logic, and a time-to-digital converter. This, together with the disconnection of defective SPADs, results in a reduction of the light-sensitive area. In addition, the pile-up of pulses, in space and in time, translates into additional efficiency losses that are inherent to digital SiPMs. The design of digital SiPMs must include some sort of optimization of the pixel architecture in order to maximize sensitivity. In this paper, we identify the most relevant variables that determine the influence of SPAD yield, fill factor loss, and spatial and temporal pile-up in the photon detection efficiency. An optimum of 8% is found for different pixel sizes. The potential benefits of molecular imaging of these optimized and small-sized pixels with independent timestamping capabilities are also analyzed.
A Mobile Platform for Movement Tracking based on a Fast-Execution-Time Optical-Flow Algorithm
R. de la Rosa-Vidal, J.A. Leñero-Bardallo, J.M. Guerrero-Rodríguez and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no.4, pp 1715-1727, 2021
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A multi-purpose mechanical platform to track moving objects in three-dimensional space has been developed. It is composed of one main microcontroller board that processes all system data, two cameras, three motors, and one secondary microcontroller board to position a platform with three degrees of freedom. The system computes the optical flow and moves the cameras accordingly, tracking motion within the visual scene. The platform operates autonomously. To the best of our knowledge, there are no similar systems reported with low-resolution image sensors and low-cost microcontrollers. Existing solutions rely on personal computers and advanced FPGAs to process image data. This article concludes that the optical flow operation is efficient even using an image sensor with very low resolution. Thus, the system complexity and image data processing are alleviated significantly. The platform can be easily adapted to different application scenarios by adding new peripherals, sensors, or image processing algorithms. A detailed description of the system design and experimental results are provided.
A Customizable Thermographic Imaging System for Medical Image Acquisition and Processing
J.A. Leñero-Bardallo, R. de la Rosa-Vidal, R. Padial-Allué, J. Ceballos-Cáceres, A. Rodríguez-Vázquez and J. Bernabéu-Wittel
Journal Paper · IEEE Sensors Journal, vol. 22, no. 17, pp 16730-16741, 2021
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A custom system has been developed for medical image acquisition and processing in both the visible and the infrared (IR) bands. Unlike some non-customizable commercial devices, this system can easily be adapted to different application scenarios by adding new peripherals and/or custom image processing algorithms. Portable, autonomous, and easy to use, it offers immediate results at the moment of examination and has a competitive cost. The system comprises a Single Board Computer (SBC) controlling a group of sensors and peripherals. The hardware implementation, described in detail in this paper, was adapted for two different application scenarios. First, the system was employed to differentiate between different kinds of vascular anomalies. The clinical results obtained are reported. The device was then redesigned to automatically detect people with high body temperatures in public environments. The system’s real-time image processing capabilities in both scenarios are demonstrated. Specific algorithms were implemented by the authors for each case study.
A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System
N. Perez-Prieto, A. Rodriguez-Vazquez, M. Alvarez-Dolado and M. Delgado-Restituto
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 5, pp 960-977, 2021
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This paper presents a high dynamic range, lowpower, low-noise mixed-signal front-end for the recording of local field potentials or electroencephalographic signals with invasive neural implants. It features time-multiplexing of 32 channels at the electrode interface for area saving and offers the ability to spatially delta encode signals to take advantage of the large correlations between nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information, thus effectively increasing the dynamic range of the system while avoiding the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro and shows an integrated input-referred noise in the 0.5200 Hz band of 1.4 Vrms for a spot noise of about 85 nV/Hz. The system draws 1.5 W per channel from 1.2 V supply and obtains 71 dB + 26 dB (with artifact compression) dynamic range, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.
Design of High-Efficiency SPADs for LiDAR Applications in 110nm CIS Technology
I. Vornicu, J.M. López-Martínez, F.N. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 21, no. 4, pp 4776-4785, 2021
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Single photon avalanche diodes (SPADs) featuring a high detection rate of near-IR photons are much desired for outdoor LiDAR based on direct time-of-flight (ToF). This article presents the complete design flow of a SPAD detector for LiDAR. First, the selection of the emitter wavelength is discussed, considering the maximum allowed power underlying eye safety regulations, solar irradiance, and reflected signal power. Then, the choice of the SPAD structure is discussed based on the TCAD simulation of quantum efficiency and crosstalk. Next, the proposed P-well/Deep N-well SPAD is explained. The electro-optical characterization of the detectors is presented as well. The performance of the time-of-flight image sensors is determined by the characteristics of the individual SPADs. To fully characterize this technology, devices with various sizes, shapes, and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is 18 V. The proposed structure has a 0.4 Hz/µ m2 dark count rate and 0.5% afterpulsing. The FWHM (total) jitter and photon detection probability at 850nm wavelength are of 92 ps and 10%. All figures have been measured at 3 V excess voltage. Finally, the performance of the SPAD detector is analyzed by evaluating the signal-to-noise ratio at different acquisition times. Distance ranging measurements have been performed, achieving a depth resolution of 1 cm up to 6.3 m range.
A Low-Resources TDC for Multi-Channel Direct ToF Readout based on a 28-nm FPGA
M. Parsakordasiabi, I. Vornicu, A. Rodríguez-Vázquez and R. Carmona-Galán
Journal Paper · Sensors, vol. 21, no. 1, article 308, 2021
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In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [-0.953, 1.185] LSB, and an integral non-linearity (INL) within [-2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.
Compact Macro-Cell with OR Pulse Combining for Low Power Digital-SiPM
I. Vornicu, F.N. Bandi, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 20, no. 21, pp 12817 - 12826, 2020
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High-density digital-Silicon Photomultipliers call for high-performance Single Photon Avalanche Diodes (SPAD) front-ends. Power consumption and fill factor are significant concerns in this kind of sensors. This paper presents a compact and power-efficient macro-cell where several SPADs share the active recharge circuitry for increased fill factor. Integrated with 110nm technology for image sensors, the array of macro-cells has 30% fill factor. Also, following the first firing of any SPAD during the same macro-pixel dead-time, the other SPADs are disabled for power saving. Of course, subsequent triggers are lost. However, they would have been masked by the OR pulse combining scheme. Besides this event-driven disabling feature, the macro-cell includes circuitry to disable noisy devices - similar to other SiPM cells. Also, the macro-cell features control of the dead-time. This paper describes the macro-cell concept, its associated analysis and design equations. Key parameters of the design are discussed to optimize power consumption. Design scalability is contemplated as well. Experimental results proved that the power efficiency of the proposed scheme depends on the illumination power. Also, power efficiency is linked to the pulse overlapping probability. For example, power saving up to 30% is obtained with 4 sub-cells per macro-cell, when pulse overlapping is about 11% for correlated light or the pulse rate per sub-cell is about 100kHz for uncorrelated light.
Comparison between Digital Tone-Mapping Operators and a Focal-Plane Pixel-Parallel Circuit
G.M.S. Nunes, F.D.V.R. Oliveira, M.C.Q. Farias, J.G. Gomes, A. Petraglia, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · Signal Processing: Image Communication, vol. 88, article 115937, 2020
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In a previous work, we proposed a color extension of an existing focal-plane tone-mapping operator (FPTMO) and introduced circuit modifications that led to smaller sensing array area and simpler off-chip white-balance operations. The proposed FPTMO chip was fabricated and its experimental test setup is under development. In the present work, we systematically compare the previously proposed FPTMOs with conventional digital tone-mapping operators (DTMOs), both in terms of overall image quality and execution time. To assess the image quality, we use the Tone-Mapped image Quality Index (TMQI) metric, the Blind Tone-Mapped Quality Index (BTMQI) metric, and an image colorfulness metric. By statistically comparing the results given by both metrics, we verify that the proposed FPTMOs achieve results similar to those obtained with DTMOs, occasionally outperforming them. To compare the tone-mapping operators execution times, we perform a detailed complexity analysis. Results show that system-level software FPTMO descriptions (FPTMO functionality described in software) rank among the fastest DTMOs and that the hardware FPTMO (described in software) speed-up depends on the target frame rate. For 30-frames-per-second color image generation, the fastest FPTMO is 15 times faster than the DTMO with highest TMQI and BTMQI metric scores, and 170 times faster than the DTMO with best colorfulness metric score.
PreVIous: A Methodology for Prediction of Visual Inference Performance on IoT Devices
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galan and A. Rodríguez-Vázquez
Journal Paper · IEEE Internet of Things Journal, vol. 7, no. 10, pp 9227-9240, 2020
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This paper presents PreVIous, a methodology to predict the performance of convolutional neural networks (CNNs) in terms of throughput and energy consumption on vision-enabled devices for the Internet of Things. CNNs typically constitute a massive computational load for such devices, which are characterized by scarce hardware resources to be shared among multiple concurrent tasks. Therefore, it is critical to select the optimal CNN architecture for a particular hardware platform according to prescribed application requirements. However, the zoo of CNN models is already vast and rapidly growing. To facilitate a suitable selection, we introduce a prediction framework that allows to evaluate the performance of CNNs prior to their actual implementation. The proposed methodology is based on PreVIousNet, a neural network specifically designed to build accurate per-layer performance predictive models. PreVIousNet incorporates the most usual parameters found in state-of-the-art network architectures. The resulting predictive models for inference time and energy have been tested against comprehensive characterizations of seven well-known CNN models running on two different software frameworks and two different embedded platforms. To the best of our knowledge, this is the most extensive study in the literature concerning CNN performance prediction on low-power low-cost devices. The average deviation between predictions and real measurements is remarkably low, ranging from 3% to 10%. This means state-of-the-art modeling accuracy. As an additional asset, the fine-grained a priori analysis provided by PreVIous could also be exploited by neural architecture search engines.
Performance Assessment of Deep Learning Frameworks through Metrics of CPU Hardware Exploitation on an Embedded Platform
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · International Journal of Electrical and Computer Engineering Systems, vol. 11, no. 1, pp 1-11, 2020
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In this paper, we analyze heterogeneous performance exhibited by some popular deep learning software frameworks for visual inference on a resource-constrained hardware platform. Benchmarking of Caffe, OpenCV, TensorFlow, and Caffe2 is performed on the same set of convolutional neural networks in terms of instantaneous throughput, power consumption, memory footprint, and CPU utilization. To understand the resulting dissimilar behavior, we thoroughly examine how the resources in the processor are differently exploited by these frameworks. We demonstrate that a strong correlation exists between hardware events occurring in the processor and inference performance. The proposed hardware-aware analysis aims to find limitations and bottlenecks emerging from the joint interaction of frameworks and networks on a particular CPU-based platform. This provides insight into introducing suitable modifications in both types of components to enhance their global performance. It also facilitates the selection of frameworks and networks among a large diversity of these components available these days for visual understanding.
Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction
R. Fiorelli, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 3, pp 606-619,2020
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This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording that Exploits the Spectral Characteristics of the Wideband Neural Signal
J.L. Valtierra, M. Delgado-Restituto, R. Fiorelli and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp 1426-1437, 2020
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This paper presents a sub- µW ac-coupled reconfigurable front-end for invasive wideband neural signal recording. The proposed topology embeds filtering capabilities enabling the selection of different frequency bands inside the neural signal spectrum. Power consumption is optimized by defining specific noise targets for each sub-band. These targets take into account the spectral characteristics of wideband neural signals: local field potentials (LFP) exhibit l/f(x) magnitude scaling while action potentials (AP) show uniform magnitude across frequency. Additionally, noise targets also consider electrode noise and the spectral distribution of noise sources in the circuit. An experimentally verified prototype designed in a standard 180 nm CMOS process draws 815 nW from a 1 V supply. The front-end is able to select among four different frequency bands (modes) up to 5 kHz. The measured input-referred spot-noise at 500 Hz in the LFP mode (1 Hz - 700 Hz) is 55 nV/root Hz while the integrated noise in the AP mode (200 Hz - 5 kHz) is 4.1 µVrms. The proposed front-end achieves sub-µW operation without penalizing other specifications such as input swing, common-mode or power-supply rejection ratios. It reduces the power consumption of neural front-ends with spectral selectivity by 6.1x and, compared with conventional wideband front-ends, it obtains a reduction of 2.5x.
A comparative study of stacked-diode configurations operating in the photovoltaic region
R. Gómez-Merchán, D. Palomeque-Mangut, J.A. Leñero-Bardallo, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 20, no. 16, pp 9105-9113, 2020
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This article presents a detailed comparative analysis of two possible stacked-diode configurations operating as solar cells. The performance of a single p-well - deep n-well diode is compared with the combination of such diode with a n-diff - pwell diode in parallel. Both configurations occupy the same area but offer different performance and, accordingly, they can have different application scopes. A test circuit to gauge the diodes performance and their spectral sensitivity has been integrated along with the two diode configurations in a 0.18 μm CMOS standard fabrication technology. The measured experimental results for the two diode configurations under study are validated with an analytical diode physical model.
Compressive Imaging using RIP-compliant CMOS Imager Architecture and Landweber Reconstruction
M. Trevisi, A. Akbari, M. Trocan, Á. Rodríguez-Vázquez and R. Carmona-Galán
Journal Paper · IEEE Transactions on Circuits and Systems for Video Technology, vol. 30, no. 2, pp 387-399, 2020
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In this paper we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in compressive sensing CMOS image sensors (CS-CIS) are recursive pseudo-random binary matrices. We have proved that the restricted isometry property (RIP) of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random numbers generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behaviour that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber (BCS-SPL) reconstruction algorithm. By means of single value decomposition (SVD) we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.
Offset-calibration with time-domain comparators using inversion-mode varactors
R. Fiorelli, M. Delgado-Restituto and A Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Brief, vol. 67, no. 1, pp 47-51, 2020
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This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.
Phase Synchronization Operator for on-chip Brain Functional Connectivity Computation
M. Delgado-Restituto, J.B. Romaine and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 5, pp 957-970, 2019
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This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters and adders. The processor, fabricated in a 0.18μm CMOS process, only occupies and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.
Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs
M. Moreno-Garcia, L. Pancheri, M. Perenzonr, R. del Rio, O. Guerra-Vinuesa and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 19, no. 14, pp 5700-5709, 2019
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The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due to their simplicity, a way to reduce the area occupied by the integrated electronics is the use of passive quenching circuits (PQCs) instead of active (AQCs) or mixed (MQCs) ones. However, the recharge phase in PQCs is slower, so the device can be retriggered before this phase ends. This paper studies the phenomena of afterpulsing and retriggering, depending on the characteristics of the SPADs and the working conditions. In order to do that, a test chip containing SPADs of different size has been characterized in several operating environments. A mathematical model has been proposed for fitting afterpulsing phenomenon. It is shown that retriggering can be also described in terms of this model, suggesting that it is linked to carriers trapped in the shallow levels of the semiconductor and that should be taken into account when considering the total amount of afterpulsing events.
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC)
A. Rodriguez-Vazquez, K. Sengupta and S. Rusu
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp 1827-1829, 2019
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This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of papers selected from those presented at the 48th ESSCIRC Conference, held at Technische Universität Dresden, Dresden, Germany, during September 3-6, 2018.
Compact Real-Time Inter-Frame Histogram Builder for 15-bits High-Speed ToF-Imagers based on Single-Photon Detection
I. Vornicu, A. Darie, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 19, no. 6, pp 2181-2190, 2019
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Time-of-flight image sensors based on single-photon detection, i.e. SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for ToF computation. This method makes use of the shifted inter-frame histogram (SifH). It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 28 words memory is enough to process histograms containing up to 215 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.
Optimum Selection of DNN Model and Framework for Edge Inference
D.Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper · IEEE Access, vol. 6, pp 51680-51692, 2018
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This paper describes a methodology to select the optimum combination of deep neural network and software framework for visual inference on embedded systems. As a first step, benchmarking is required. In particular, we have benchmarked six popular network models running on four deep learning frameworks implemented on a low-cost embedded platform. Three key performance metrics have been measured and compared with the resulting 24 combinations: accuracy, throughput, and power consumption. Then, application-level specifications come into play. We propose a figure of merit enabling the evaluation of each network/framework pair in terms of relative importance of the aforementioned metrics for a targeted application. We prove through numerical analysis and meaningful graphical representations that only a reduced subset of the combinations must actually be considered for real deployment. Our approach can be extended to other networks, frameworks, and performance parameters, thus supporting system-level design decisions in the ever-changing ecosystem of embedded deep learning technology.
Optimum Network/Framework Selection from High-Level Specifications in Embedded Deep Learning Vision Applications
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · Lecture Notes in Computer Science LNCS, vol. 11182, pp 369-379, 2018
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This paper benchmarks 16 combinations of popular Deep Neural Networks and Deep Learning frameworks on an embedded platform. A Figure of Merit based on high-level specifications is introduced. By sweeping the relative weight of accuracy, throughput and power consumption on global performance, we demonstrate that only a reduced set of the analyzed combinations must actually be considered for real deployment. We also report the optimum network/framework selection for all possible application scenarios defined in those terms, i.e. weighted balance of the aforementioned parameters. Our approach can be extended to other networks, frameworks and performance parameters, thus supporting system-level design decisions in the ever-changing ecosystem of Deep Learning technology.
Applications of event-based image sensors - Review and analysis
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 46, no. 9, pp 1620-1630, 2018
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The spread of event-driven asynchronous vision sensors during the last years has increased significantly the industrial interest and the application scenarios for them. This article reviews the main fields of application that event-based image sensors have found during the last 20 years. We focus in the description of applications where such devices can outperform conventional frame-based sensors. The practical functions of the three main families of asynchronous event-based sensors are analyzed. The article also studies what are the factors that increase nowadays the demand of sensors that minimize the power and bandwidth consumption. Moreover, the technological factors that have facilitated the development of asynchronous sensors are discussed.
Asynchronous spiking pixel with programmable sensitivity to illumination
J.A. Leñero-Bardallo, M. Delgado-Restituto, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp 3854-3863, 2018
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A spiking pixel to be used in image sensor arrays for asynchronous frame-based operation is presented. The pixel features both local and global adaptive sensitivity to the illumination level. Local adaptation is performed by adjusting the voltage stored in an embedded analog memory according to the average illumination within a neighborhood. Global adaptation to the overall illumination of the array is implemented by adjusting a voltage value common to all the pixels. These programming capabilities allow full control on the sensor sensitivity, pixel output data flow, and energy consumption, thus, overcoming the limitations observed in current image sensors based on spiking pixels. Experimental results validate the functionality of the proposal.
On the analysis and detection of flames with an asynchronous spiking image sensor
J.A. Leñero-Bardallo, J.M. Guerrero-Rodríguez, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 18, no. 16, pp 6588-6595, 2018
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We have investigated the capabilities of a custom asynchronous spiking image sensor operating in the Near Infrared (NIR) band to study flame radiation emissions, monitor their transient activity, and detect their presence. Asynchronous sensors have inherent capabilities, i.e. good temporal resolution, high dynamic range, and low data redundancy. This makes them competitive against Infrared (IR) cameras and CMOS frame-based NIR imagers. In the article, we analyze, discuss and compare the experimental data measured with our sensor against results obtained with conventional devices. A set of measurements have been taken to study the flame emission levels and their transient variations. Moreover, a flame detection algorithm, adapted to our sensor asynchronous outputs, has been developed. Results show that asynchronous spiking sensors have an excellent potential for flame analysis and monitoring.
CMOS Vision Sensors: Embedding Computer Vision at Imaging Front-Ends
A. Rodríguez-Vázquez, J. Fernández-Berni, J.A. Leñero-Bardallo, I. Vornicu and R. Carmona-Galán
Journal Paper · IEEE Circuits and Systems Magazine, vol. 18, no. 2, pp 90-107, 2018
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CMOS Image Sensors (CIS) are key for imaging technologies. These chips are conceived for capturing optical scenes focused on their surface, and for delivering electrical images, commonly in digital format. CISs may incorporate intelligence; however, their smartness basically concerns calibration, error correction and other similar tasks. The term CVISs (CMOS VIsion Sensors) defines other class of sensor front-ends which are aimed at performing vision tasks right at the focal plane. They have been running under names such as computational image sensors, vision sensors and silicon retinas, among others. CVIS and CISs are similar regarding physical implementation. However, while inputs of both CIS and CVIS are images captured by photo-sensors placed at the focal-plane, CVISs primary outputs may not be images but either image features or even decisions based on the spatial-temporal analysis of the scenes. We may hence state that CVISs are more ‘intelligent’ than CISs as they focus on information instead of on raw data. Actually, CVIS architectures capable of extracting and interpreting the information contained in images, and prompting reaction commands thereof, have been explored for years in academia, and industrial applications are recently ramping up. One of the challenges of CVISs architects is incorporating computer vision concepts into the design flow. The endeavor is ambitious because imaging and computer vision communities are rather disjoint groups talking different languages. The Cellular Nonlinear Network Universal Machine (CNNUM) paradigm, proposed by Profs. Chua and Roska, defined an adequate framework for such conciliation as it is particularly well suited for hardware-software co-design. This paper overviews CVISs chips that were conceived and prototyped at IMS E Vision Lab over the past twenty years. Some of them fit the CNNUM paradigm while others are tangential to it. All of them employ per-pixel mixed-signal processing circuitry to achieve sensor-processing concurrency in the quest of fast operation with reduced energy budget.
Real-Time Inter-Frame Histogram Builder for SPAD Image Sensors
I. Vornicu, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 18, no. 4, pp 1576-1584, 2018
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CMOS image sensors based on single-photon avalanche-diodes (SPAD) are suitable for 2D and 3D vision. Limited by uncorrelated noise and/or low illumination conditions, image capturing becomes nearly impossible in a single-shot exposure time. Moreover the depth accuracy is affected by jitter. Therefore, many frames need to be taken to reconstruct the final accurate image. The proposed reconstruction algorithm is based on pixel-wise histogram building. Specifically, a histogram is built on the fly for each pixel of the array from the ongoing acquired frames. This paper presents the design and implementation on FPGA of a real-time pixel-wise inter-frame histogram builder at 1kfps. The design has been proven with a 64×64-pixels SPAD camera. Its remarkable robustness has been demonstrated in harsh conditions such as 42 kHz of dark count rate (DCR) and high background illumination up to 20 times larger than the DCR. The system has a graphic user interface for 2D/3D imager configuration, image streaming and pixel-wise histogram streaming.
Highly Scalable Real Time Epilepsy Diagnosis Architecture Via Phase Correlation
J.B. Romaine, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Procedia Technology, vol. 27, pp 55-56, 2017
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Epilepsy is at current the world´s second most common neurological disorder affecting an estimated 50 million people. While up to 70% of epileptic suffers are treated successfully with epileptic medication some 30% continue to suffer untreated. This gap could be filled by the implementation of implantable neural prostheses which are able to detect when a seizure is coming and eventually actuate in the brain to stop its progression.
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
I. Vornicu, R. Carmona-Galan and Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 11, pp 2821-2834, 2017
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Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper, we are covering the modeling, design, and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64x64-pixel array. It has been fabricated in a 0.18 mu m standard CMOS technology. Occupation area is 28x29 mu m(2) and power consumption is 1.17 mW at 850 MHz. The measured gain of the VCRO is of 477 MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely, from 400 to 850 MHz. The phase noise is of -102 dBc/Hz at 2 MHz offset frequency from 850 MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147 ps with a rms DNL/INL of 0.13/1.7LSB.
Sun sensor based on a luminance spiking pixel array
J.A. Lenero-Bardallo, L. Farian, J.M. Guerrero-Rodriguez, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 17, no. 20, pp 6578-6588, 2017
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We present a novel sun sensor concept. It is the very first sun sensor built with an Address Event Representation (AER) spiking pixel matrix. Its pixels spike with a frequency proportional to illumination. It offers remarkable advantages over conventional digital sun sensors based on Active Pixel Sensor (APS) pixels. Its output data flow is quite reduced. It is possible to resolve the sun position just receiving one single event operating in Time-to-First-Spike (TFS) mode. It operates with a latency in the order of milliseconds. It has higher dynamic range than APS image sensors (higher than 100dB). A custom algorithm to compute the centroid of the illuminated pixels is presented. Experimental results are provided.
Gaussian Pyramid: Comparative Analysis of Hardware Architectures
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 9, pp 2308-2321, 2017
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This paper addresses a comparison of architectures for the hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor front-end. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded preprocessing structures for Gaussian spatial filtering. This later choice belongs to the general category of " artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. This paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs, single-slope, SAR, cyclic, Sigma Delta, and pipeline, and the number of digital processors. Results show that speed and energy advantages of preprocessing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.
Compensation of PVT Variations in ToF Imagers with In-Pixel TDC
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · Sensors, vol. 17, no. 5, article 1072, 2017
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The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must contemplate system-level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on-chip. The main building block of the PLL is a voltage-controlled ring-oscillator (VCRO) that is identical to the ones employed for the in-pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time-of-flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 °C to 100 °C; (ii) 27% down to 0.27%, when the voltage supply changes within ±10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters´ variation.
A Wide Linear Dynamic Range Image Sensor Based on Asynchronous Self-Reset and Tagging of Saturation Events
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp 1605-1617, 2017
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We report a high dynamic range (HDR) image sensor with a linear response that overcomes some of the limitations of sensors with pixels with self-reset operation. It operates similar to an active pixel sensor, but its pixels have a novel asynchronous event-based overflow detection mechanism. Whenever the pixel voltages at the integration capacitance reach a programmable threshold, the pixels self-reset and send out asynchronously an event indicating this. At the end of the integration period, the voltage at the integration capacitance is digitized and readout. Combining this information with the number of events fired by each pixel, it is possible to render linear HDR images. Event operation is transparent to the final user. There is no limitation for the number of self-resets of each pixel. The output data format is compatible with frame-based devices. The sensor was fabricated in the AMS 0.18-μm HV technology. A detailed system description and experimental results are provided in this paper. The sensor can render images with an intra-scene dynamic range of up to 130 dB with linear outputs. The pixels' pitch is 25 μm and the sensor power consumption is 58.6 mW.
TFET-based Well Capacity Adjustment in Active Pixel Sensor for Enhanced High Dynamic Range
J. Fernández-Berni, M. Niemier, X.S. Hu, H. Lu, W. Li, P. Fay, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · Electronics Letters, vol.53, no. 9, pp 622-624, 2017
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A tunnel field-effect transistor (TFET)-based pixel circuit for well capacity adjustment that does not require subthreshold operation on the part of the reset transistor is presented. In CMOS, this subthreshold operation leads to temporal noise, distortion and fixed pattern noise, becoming a primary limiting performance factor. In the proposed circuit, the asymmetric conduction associated with TFETs is exploited. This property, arising from the inherent physical structure of the device, provides the selective well adjustments during photo-integration which are demanded for achieving high dynamic range. A GaN-based heterojunction TFET has been designed according to the specific requirements for this application.
A switched-capacitor skew-tent map implementation for random number generation
J.L. Valtierra, E. Tlelo-Cuautle and A. Rodriguez-Vazquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 305-315, 2017
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Piecewise linear one-dimensional maps have been proposed as the basis for low-power analog and mixed-signal true random number generators (TRNGs). Recent research has moved towards conceiving maps that operate robustly under the consideration of parameter variations. In this paper, we introduce an oscillator circuit mapping a low-complexity map known as the skew-tent. This oscillator is employed as the basis for a TRNG scheme. Simulation results in TSMC 0.18 μm validate the chaotic oscillator and the randomness of the TRNG scheme is verified with the NIST test suite 800-22.
A CMOS Digital SiPM with Focal-Plane Light-Spot Statistics for DOI Computation
I. Vornicu, F.N. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 17, no. 3, pp 632-643, 2017
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Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This paper contemplates the computation of DOI based on the standard deviation of the light distribution. The simulations have been carried out by GAMOS. The design of the proposed digital silicon photomultiplier (d-SiPM) with focal plane detection of the center of mass position and dispersion of the scintillation light is presented. The d-SiPM shares the same off-chip time-to-digital converter such that each pixel can be individually connected to it. A miniature d-SiPM 8×8 single-photon avalanche-diode (SPAD) array has been fabricated as a proof of concept. The SPADs along each row and column are connected through an OR combination technique. It has 256×256μm2 without peripherals circuits and pads. The fill factor is about 11%. The average dark count rate of the mini d-SiPM is of 240 kHz. The average photon detection efficiency is 5% at 480 nm wavelength, room temperature, and 0.9 V excess voltage. The dynamic range is of 96 dB. The sensor array features a time resolution of 212 ps. The photon-timing SNR is 81 dB. The focal plane statistics of the light-spot has been proved as well by measurements.
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodriguez-Perez, A. Darie, C. Soto-Sánchez, E. Fernandez-Jover and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 2, pp 420-433, 2017
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This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.
Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction
M. Suárez, V.M. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp 483-495, 2017
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This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits having the same response regardless of the distance of the scene to the camera. The chip comprises 176 x 120 photosensors arranged into 88 x 60 processing elements (PEs). The Gaussian pyramid is generated with a double-Euler switched capacitor (SC) network. Every PE comprises four photodiodes, one 8 b single-slope analog-to-digital converter, one correlated double sampling circuit, and four state capacitors with their corresponding switches to implement the double-Euler SC network. Every PE occupies 44 x 44 μm^2. Measurements from the chip are presented to assess the accuracy of the generated Gaussian pyramid for visual tracking applications. Error levels are below 2% full-scale output, thus making the chip feasible for these applications. Also, energy cost is 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions of imager plus microprocessor unit.
Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes
J.A. Lenero-Bardallo, M. Delgado-Restituto, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 16, no. 23, pp 8448-8455, 2016
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We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel versus conventional ones made with single p/n junctions. We propose a method to characterize and compare photodiodes sensitivity. For this purpose, a dedicated chip in the standard AMS 180-nm HV technology has been fabricated. Four different sensor structures were implemented and compared. Experimental results are provided. Measurements show sensitivity enhancement ranging from 55% to 70% within the 500-1100 nm spectral region. The larger increment is happening in the near infrared band (up to 62%). Such results make stacked photodiodes suitable candidates for the implementation of photosensors in vision chips designed for standard CMOS technologies.
Image Sensing Scheme Enabling Fully-Programmable Light Adaptation and Tone Mapping with a Single Exposure
J. Fernández-Berni, F.D.V.R. Oliveira, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 16, no. 13, pp. 5121-5122, 2016
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This letter presents new insights into a high dynamic range (HDR) technique recently reported. We demonstrate that two intertwined photodiodes per pixel can perform tone mapping under unconstrained illumination conditions with a single exposure. Experimental results attained from a prototype chip confirm the proposed theoretical framework. It opens the door to the realization of imagers providing HDR images free of artifacts without requiring any digital post-processing at all.
Single-Exposure HDR Technique Based on Tunable Balance Between Local and Global Adaptation
J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 5, pp. 488-492, 2016
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This brief describes a high-dynamic-range technique that compresses wide ranges of illuminations into the available signal range with a single exposure. An online analysis of the image histogram provides the sensor with the necessary feedback to dynamically accommodate changing illumination conditions. This adaptation is accomplished by properly weighing the influence of local and global illuminations on each pixel response. The main advantages of this technique with respect to similar approaches previously reported are as follows: 1) standard active-pixel-sensor circuitry can be used to render the pixel values and 2) the resulting compressed image representation is ready either for readout or for early vision processing at the very focal plane without requiring any additional peripheral circuit block. Experimental results from a prototype smart image sensor achieving a dynamic range of 102 dB are presented.
A Bio-Inspired Vision Sensor with Dual Operation and Readout Modes
J.A. Leñero-Bardallo, P. Häfliger, R. Carmona-Galán and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 16, no. 2, pp. 317-330, 2016
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This paper presents a novel event-based vision sensor with two operation modes: 1) intensity mode and spatial contrast detection. They can be combined with two different readout approaches: 1) pulse density modulation and time-to-first spike. The sensor is conceived to be a node of an smart camera network made up of several independent an autonomous nodes that send information to a central one. The user can toggle the operation and the readout modes with two control bits. The sensor has low latency (below 1 ms under average illumination conditions), low power consumption (19 mA), and reduced data flow, when detecting spatial contrast. A new approach to compute the spatial contrast based on inter-pixel event communication less prone to mismatch effects than diffusive networks is proposed. The sensor was fabricated in the standard AMS4M2P 0.35-μm process. A detailed system-level description and experimental results are provided.
Compact CMOS active quenching/recharge circuit for SPAD arrays
I. Vornicu, R. Carmona-Galán, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 44, no. 4, pp 917-928, 2016
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Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recherge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12 μm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break-down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post- layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse-width jitter is below 1.8 ns when dead time is set to 40 ns.
Time interval generator with 8 ps resolution and wide range for large TDC array characterization
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 87, no. 2, pp 181-189, 2016
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Accurate generation of picosecond-resolution wide-range time intervals gives rise to a new time-efficient method for the characterization of large arrays of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20 ps RMS jitter for a pulse width ranging from 600 ps to 33 μs. The incremental time resolution is 8 ps and the repetition rate is up to 2 MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27 ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field. The measurement results of the time-to-digital converter array driven by the designed digital-to-time converter module are presented as well. The effectiveness of the proposed method is evaluated by comparing it with the statistical code density test.
On-chip time-of-flight estimation in standard CMOS technology
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper · SPIE Newsroom, Published online Feb 2015
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In the last decade, CMOS image sensors (CISs) have reached a considerable level of maturity and their performance is now comparable with CCD sensors, in terms of image quality. CISs have almost completely replaced CCDs in commercial photo cameras and mobile phones. The main advantage of using CMOS technology is the possibility of integrating additional intelligence at the sensor level. Complex image processing algorithms can be run on-chip at high frame rates. A possible future development for CIS technology is to capture 3D information from a scene. This, however, requires active illumination schemes.
A 151 dB high dynamic range CMOS image sensor chip architecture with tone mapping compression embedded in-pixel
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 15, no. 1, pp 180-195, 2015
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This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone mapping algorithm during image capture operation. The histogram of the previous frame of an auxiliary image, which contains time stamp information, is employed as an estimation of the probability of illuminations impinging pixels at the present frame. The compression function of illuminations, namely tone mapping curve, is calculated using this histogram. A QCIF resolution proof-of-concept prototype has been fabricated using a 0.35 μm opto-flavored standard technology. The sensor is capable of mapping scenes with a maximum intra-frame dynamic range of 151 dB (25 bits/pixel in linear representation) by compressing them to only 7 bits/pixel, while keeping visual quality in details and contrast. The in-pixel on-the-fly fully parallel tone mapping achieves high-frame rate allowing real-time high dynamic range video (120 dB at 30 frames/s).
Bottom-up performance analysis of focal-plane mixed-signal hardware for Viola-Jones early vision tasks
J. Fernández-Berni, R. Carmona-Galán, R. del Río and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 43, no. 8, pp 1063-1079, 2015
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Focal-plane mixed-signal arrays have traditionally been designed according to the general claim that moderate accuracy in processing is affordable. The performance of their circuitry has been analyzed in these terms without a comprehensive study of the ultimate consequences of such moderate accuracy. In this paper, for the first time to the best of our knowledge, we do carry out this study. We move expectable performance of mixed-signal image processing hardware directly into the vision algorithm making use of it. This permits to close a wider design loop, enabling a more aggressive design of this kind of hardware provided that the algorithm, at the highest level -semantic interpretation of the scene-, can afford it. Thus, we present a thorough analysis of the non-idealities associated with the implementation of a QVGA array tailored for the distinctive characteristics of the Viola-Jones processing framework. The resulting deviation models are then introduced in the processing flow of this framework provided by the OpenCV library. We have found, contrary to what could be expected, that these deviations do not necessarily degrade the performance of the Viola-Jones algorithm. They could be even beneficial for certain high-level specifications. Additionally, we demonstrate the architectural advantages of our approach: exploitation of focal-plane distributed memory and ultra-low-power operation.
A CMOS imager for time-of-flight and photon counting based on single photon avalanche diodes and in-pixel time-to-digital converters
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper · Romanian Journal of Information Science and Technology, vol. 17, no. 4, pp 353-371, 2014
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The design of a CMOS image sensor based on single-photon avalanche-diode (SPAD) array with in-pixel time-to-digital converter (TDC) is presented. The architecture of the imager is thoroughly described with emphasis on the characterization of the TDCs array. It is targeted for 3D image reconstruction. Several techniques as fast quenching/recharge circuit with tunable dead-time and time gated-operation are applied to reduce the noise and the power consumption. The chip was fabricated in a 0.18 μm standard CMOS process and implements a double functionality: time-of-flight (ToF) estimation and photon counting. The imager features a programmable time resolution of the array of TDCs down to 145 ps. The measured accuracy of the minimum time bin is lower than ± 1LSB DNL and ± 1.7 LSB INL. The TDC jitter over the full dynamic range is less than 1 LSB.
High dynamic range adaptation for ROI tracking based on reconfigurable concurrent dual-sensing
J. Fernández-Berni, R. Carmona-Galán, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Electronics Letters, vol. 50, no. 24, pp 1832-1834, 2014
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A single-exposure technique to extend the dynamic range of vision sensors is presented. It is particularly suitable for vision algorithms requiring region-of-interest (ROI) tracking under varying illumination conditions. The operation is supported by two intertwined photodiodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal plane into independent regions within which automatic concurrent adjustment of the integration time takes place for each frame. At pixel level, one of the photodiodes senses the pixel value itself, whereas the other, in collaboration with its counterparts in every prescribed ROI, senses the mean illumination of that specific ROI. An additional circuitry interconnecting both photodiodes asynchronously determines the integration period for each ROI according to its mean illumination. The experimental results for a quarter video graphics array prototype CMOS vision sensor are reported.
Equalization-based digital background calibration technique for pipelined ADCs
B. Zeinali, T. Moosazadeh, M. Yavari and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp 322-333, 2014
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In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC.
Focal-plane sensing-processing: A power-efficient approach for the implementation of privacy-aware networked visual sensors
J. Fernandez-Berni, R. Carmona-Galan, R. del Rio, R. Kleihorst, W. Philips and A. Rodriguez-Vazquez
Journal Paper · Sensors, vol. 14, no. 8, pp. 15203-15226, 2014
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The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image sensors pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. Power consumption also constitutes a crucial aspect. Images contain a massive amount of data to be processed under strict timing requirements, demanding high-performance vision systems. In this paper, we describe a hardware-based strategy to concurrently address these two key issues. By conveying processing capabilities to the focal plane in addition to sensing, we can implement privacy protection measures just at the point where sensitive data are generated. Furthermore, such measures can be tailored for efficiently reducing the computational load of subsequent processing stages. As a proof of concept, a full-custom QVGA vision sensor chip is presented. It incorporates a mixed-signal focal-plane sensing-processing array providing programmable pixelation of multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise dynamic range adaptation, integral image computation and multi-resolution filtering. The proposed circuitry is also suitable to build a granular space, becoming the raw material for subsequent feature extraction and recognition of categorized objects.
Tunable low noise amplifier implementation with low distortion pseudo-resistance for in Vivo Brain activity Measurement
Z. Karasz, R. Fiath, P. Foldesy and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 14, no. 5, 2014
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This paper presents a low power neural signal amplifier with tunable cut-off frequencies. The presented compact amplifier, which is used for sensing various types of neural signals, reduces the size and the power consumption of the whole circuit. The distinguishing features of this solution are the large time constant, linearity, and small achievable area, which are realized with a configurable series of pseudo resistances. The proof of concept has been manufactured on TSMC 90nm technology.
Special Issue on Advances in sensing and communication circuits (ICECS 2012)
A. Rodríguez-Vázquez, J. Fernández-Berni and J.M. de la Rosa
Journal Paper · Analog Integrated Circuits and Signal Processing , vol. 77, no. 3, pp 315-317, 2013
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Abstract not available
A tone mapping algorithm for acquisition of high dynamic range images using event-driven adaptive digital CMOS pixels
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 77, no. 3, pp 401-413, 2013
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An algorithm for the tone mapping of high dynamic range (HDR) scenes in digital CMOS pixels has been developed. The algorithm performs a content-aware compression over HDR scenes, which produces a representation of several decades of acquired data while keeping the main contents in the scene using only 7-bits/pixel.
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
R. Carmona-Galán, Á. Zarándy, C. Rekeczky, P. Földesy, A. Rodríguez-Pérez, C. Domínguez-Matas, J. Fernández-Berni, G. Liñán-Cembrano, B. Pérez-Verdú, Z. Kárász, M. Suárez-Cambre, V. Brea-Sánchez, T. Roska, Á. Rodríguez-Vázquez
Journal Paper · Journal of Systems Architecture, vol. 59, no. 10 part A, pp 908-919, 2013
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This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15 μm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.
Ultralow-power processing array for image enhancement and edge detection
J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 11, pp 751-755, 2012
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This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be turned into anisotropic by a very simple voltage comparator between neighboring nodes whose output controls the gate of the elementary MOS resistor. Anisotropic diffusion enables image enhancement by removing noise and small local variations while preserving edges. A binary edge image can also be attained by combining the output of the voltage comparators. In addition to these processing capabilities, the simulations have confirmed the robustness of the array against process variations and mismatch. The power consumption extrapolated for VGA-resolution array processing images at 30 fps is 570 μW.
Early forest fire detection by vision-enabled wireless sensor networks
J. Fernández-Berni, R. Carmona-Galán, J.F. Martínez-Carmona and A. Rodríguez-Vázquez
Journal Paper · International Journal of Wildland Fire, vol. 21, no. 8, pp 938-949, 2012
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Wireless sensor networks constitute a powerful technology particularly suitable for environmental monitoring. With regard to wildfires, they enable low-cost fine-grained surveillance of hazardous locations like wildland-urban interfaces. This paper presents work developed during the last 4 years targeting a vision-enabled wireless sensor network node for the reliable, early on-site detection of forest fires. The tasks carried out ranged from devising a robust vision algorithm for smoke detection to the design and physical implementation of a power-efficient smart imager tailored to the characteristics of such an algorithm. By integrating this smart imager with a commercial wireless platform, we endowed the resulting system with vision capabilities and radio communication. Numerous tests were arranged in different natural scenarios in order to progressively tune all the parameters involved in the autonomous operation of this prototype node. The last test carried out, involving the prescribed burning of a 9520-m shrub plot, confirmed the high degree of reliability of our approach in terms of both successful early detection and a very low false-alarm rate. Journal compilation.
CMOS-3D Smart Imager Architectures for Feature Detection
V.M. Brea, J. Fernández-Berni, R. Carmona-Galán, G. Liñán, D. Cabello and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 4, pp 723-736, 2012
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This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.
Behavioral modeling of pipeline ADC building blocks
J. Ruiz-Amaya, M. Delgado Restituto and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications vol. 40, no. 6, pp 571-594, 2012
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This paper presents accurate behavioral models for the basic building blocks of pipeline data converters with emphasis on the MDAC circuit. These models take into account major circuit-level non-idealities, including small- and large-signal effects, as well as the impact of switch-on resistance effects and thermal noise contributions. The behavioral models have been validated against transistor-level simulations under different scenarios, showing in all cases a worst-case deviation of 0.3 bit effective resolution. Copyright © 2011 John Wiley & Sons, Ltd.
A low-power programmable neural spike detection channel with embedded calibration and data compression
A. Rodríguez-Pérez, J. Ruíz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 2, pp 87-100, 2012
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This paper reports a programmable 400 um pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 uVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 uW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 uW when the feature extraction mode is enabled.
A 1.2V 10-bit 60-MS/s 23mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 71, no. 3, pp 371-381, 2012
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A 1.2 V 10-bit 60 MS/s pipeline Analog-to-Digital Converter (ADC), fabricated in a 130 nm CMOS technology, is presented. The prototype is composed by five 3-bit pipeline stages and a Sample and Hold (S&H) circuit at the front. Two-stage Miller-compensated Operational Transconductance Amplifiers (OTAs), offset-compensated comparators and bootstrapping sampling switches have been used due to the low voltage supply requirements. Special attention has been paid to the reduction of the power consumption using a thorough design methodology. The converter only consumes 23 mW including on-chip reference voltages and bias current generators. The differential and integral nonlinearity of the ADC are below 0.60 and 0.61 LSBs, respectively. The pipeline converter achieves an effective resolution above 9 bits along the Nyquist bandwidth, and obtains 0.67 pJ energy consumption per conversion, making it one of the most energy-efficient 10-bit video-rate pipeline ADC reported to date. © 2011 Springer Science+Business Media, LLC.
IC-constrained optimization of continuous-time Gm-C filters
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 40, no. 2, pp 127-143, 2012
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This paper presents an automated synthesis procedure for integrated continuous-time fully-differential Gm-C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB (R) framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright (C) 2010 John Wiley & Sons, Ltd.
An ultralow-power mixed-signal back end for passive sensor UHF RFID transponders
J.A. Rodríguez-Rodríguez, M. Delgado-Restituto, J. Masuch, A. Rodríguez-Pérez, E. Alarcón and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Industrial Electronics, vol. 59, no. 2, pp 1310-1322, 2012
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This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35-mu m CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 x 10(-3) with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 mu A from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.
Transistor-level synthesis of pipeline analog-to-digital converters using a design-space reduction algorithm
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 58, no. 12, pp 2816-2828, 2011
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A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 mu m CMOS 10 bits@ 60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@ 1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@ 1.2 V and an effective resolution of 9.47-bit@ 1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.
Introduction to the special issue on the 36th European Solid-State Circuits Conference (ESSCIRC)
A. Rodríguez-Vázquez, D.M.W. Leenaerts and J.P. de Gyvez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp 1519-1521, 2011
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The 22 papers in this special issue were originally presented at the 2010 European Solid-State Circuits Conference (ESSCIRC). The conference was jointly organized with the European Solid-State Device Research Conference and held September 14-16 in Seville, Spain. Papers cover the traditional ESSCIRC topics of analog circuits, digital circuits, data converters, sensors and imagers, and communications and RF circuits. Energy harvesting and biomedical circuits were also within ESSCIRC 2010 topics and are represented in this issue.
Integrated circuitry to detect slippage inspired by human skin and artificial retinas
R. Maldonado-López, F. Vidal-Verdú, G. Liñán and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 8, pp 1554-1565, 2009
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This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage via the data provided by a tactile sensor. Some implementations use different layers of piezoresistive and piezoelectric materials to build upon the raw sensor and obtain the static (pressure) as well as the dynamic (slippage) information. In this paper, a simple raw sensor is used, and a circuitry is implemented, which is able to extract the dynamic information from a single piezoresistive layer. The circuitry was inspired by structures found in human skin and retina, as they are biological systems made up of a dense network of receptors. It is largely based on an artificial retina [22], which is able to detect motion by using relatively simple spatial temporal dynamics. The circuitry was adapted to respond in the bandwidth of microvibrations produced by early slippage, resembling human skin. Experimental measurements from a chip implemented in a 0.35-m four-metal two-poly standard CMOS process are presented to show both the performance of the building blocks included in each processing node and the operation of the whole system as a detector of early slippage.
Accurate settling-time modeling and design procedures for two-stage miller-compensated amplifiers for switched-capacitor circuits
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 6, pp 1077-1087, 2009
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We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.
Bridging technology innovations to foundations, special issue ECCTD 2007
M. Delgado-Restituto, E. Alarcon and A. Rodríguez-Vázquez (Guest Eds.)
Journal Paper · International Journal of Circuit Theory and Applications, vol. 37, no. 2, pp 159-161, 2009
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Abstract not available
Insect-vision inspired collision warning vision processor for automobiles
G. Liñán-Cembrano, L. Carranza, C. Rind, A. Zarandy, M. Soininen and A. Rodríguez-Vázquez
Journal Paper · IEEE Circuits and Systems Magazine, vol. 8, no. 2, pp 6-24, 2008
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Vision is expected to play important roles for car safety enhancement. Imaging systems can be used to enlarging the vision field of the driver. For instance capturing and displaying views of hidden areas around the car which the driver can analyze for safer decision-making. Vision systems go a step further. They can autonomously analyze the visual information, identify dangerous situations and prompt the delivery of warning signals. For instance in case of road lane departure, if an overtaking car is in the blind spot, if an object is approaching within collision course, etc. Processing capabilities are also needed for applications viewing the car inteRíor such as "intelligent airbag systems" that base deployment decisions on passenger features. On-line processing of visual information for car safety involves multiple sensors and views, huge amount of data per view and large frame rates. The associated computational load may be prohibitive for conventional processing architectures. Dedicated systems with embedded local processing capabilities may be needed to confront the challenges. This paper describes a dedicated sensory-processing architecture for collision warning which is inspired by insect vision. Particularly, the paper relies on the exploitation of the knowledge about the behavior of Locusta Migratoria to develop dedicated chips and systems which are integrated into model cars as well as into a commercial car (Volvo XC90) and tested to deliver collision warnings in real traffic scenaríos.
Matrix methods for the dynamic range optimization of continuous-time G(m)-C filters
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 55, no. 9, pp 2525-2538, 2008
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This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential G(m)-C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. Using these methods, an analytical technique for the dynamic range optimization of weakly nonlinear G(m)-C filters under power dissipation constraints is presented. The procedure is first explained for general filter structures and then illustrated with a simple biquadratic section.
Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform
R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · Microelectronics Journal, vol. 39, no. 1, pp 137-151, 2008
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This paper presents a detailed study of the clock jitter error in multi-bit continuous-time EA modulators with non-return-to-zero feedback waveform. It is demonstrated that jitter-induced noise power can be separated into two main components: one that depends on the modulator loop-filter transfer function and the other dependent on input signal parameters, i.e. amplitude and frequency. The latter component, not considered in previous approaches, allows us accurately to predict the resolution loss caused by jitter, showing effects not taken into account previously in literature despite the fact that they are especially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Closed-form expressions are derived for in-band error power and signal-to-noise ratio that can be used to optimize modulator performance in terms of jitter insensitivity. Time-domain simulations of several modulator topologies (both single-loop and cascade) intended for VDSL application demonstrate the validity of the presented approach. (c) 2007 Elsevier Ltd. All rights reserved.
Systematic design of high-resolution high-frequency cascade continuous-time sigma-delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, E. Roca, A. Rodríguez Vázquez and F.V. Fernández
Journal Paper · ETRI Journal, vol. 30, no. 4, pp 535-545, 2008
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This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigma-delta (SIGMA DELTA) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT SIGMA DELTA modulator in a 1.2 V 130 nm CMOS technology.
Early slip detection with a tactile sensor based on retina
R. Maldonado-López, F. Vidal-Verdú, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 53, no. 2-3, pp 97-108, 2007
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The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The array of pressure data provided by these devices can be treated with different image processing algorithms to extract miscellaneous information. However, as in the case of vision chips or artificial retinas, problems arise when the size of the array and the computational complexity increase. Having a look at the skin, the information collected by every mechanoreceptor is not sent to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks, as the case of slip detection with tactile sensors, which is demanding in computing requirements. Here we show some results from a tactile processor based on circuitry proposed for an artificial retina that has been modified to mimic the way the biological skin works.
A new high-level synthesis methodology of cascaded continuous-time sigma delta modulators
R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp 739-743, 2006
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This brief presents an efficient method for synthesizing cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to placing the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and. robustness with respect to circuit errors.
Double-sampling single-loop Sigma Delta modulator topologies for broad-band applications
M. Yavari, O. Shoaei and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 4, pp 314-318, 2006
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This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement.
An approach to the design of cascade sigma delta modulators for multistandard wireless transceivers
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · WSEAS Transactions on Circuits and Systems, vol. 4, no. 12, pp 1811-1818, 2005
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This paper discusses issues concerning the design of reconfigurable cascade sigma-delta modulators for multistandard wireless transceivers. The use of an expandible cascade modulator is considered as the starting point to boost reconfigurability at the architectural level. Then, a top-down methodology is proposed to obtain the cascade candidates that better fulfil the requirements of each standard with adaptive power consumption, taking into account the complexity of the reconfiguration at both architecture- and circuit-level. Several reconfiguration strategies are presented and validated by time-domain behavioural simulations.
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs
J.M. de la Rosa, S. Escalera, B. Pérez-Verdú, F. Medeiro, O. Guerra, R. del Río and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp 2246-2264, 2005
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This paper describes a 0.35-mu m CMOS chopper-stabilized switched-capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0.5, x 1, x 2, and x 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 degrees C to 175 degrees C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm(2) silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution Sigma Delta modulators.
High-level synthesis of switched-capacitor, switched-current and continuous-time sigma delta modulators using SIMULINK-based time-domain behavioral models
J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernández, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 9, pp 1795-1810, 2005
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This paper presents a high-level synthesis tool for Sigma Delta modulators (Sigma Delta Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for Sigma Delta M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Sigma Delta Ms using both discrete-time and continuous-time circuit techniques.
Synthesis of a wireless communication analog back-end based on a mismatch-aware symbolic approach
R. Castro-López, O. Guerra, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 40, no. 3, pp 215-233, 2004
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In this paper, a methodology to automate the synthesis of an industrial-purpose analog integrated circuit, namely the back-end of an I&Q transmit interface, is presented. A good matching between both I and Q channels is desirable to ensure the correct circuit functioning. The proposed methodology combines the use of symbolic expressions with numerical approaches. While the symbolic expressions allow a fast iterative evaluation of the circuit performance, the numerical capabilities ensure a rapid optimization of the results. Unlike other approaches, the methodology uses symbolic expressions explicitly considering device mismatch, which are evaluated performing a Monte-Carlo analysis. The expressions have been obtained using an error-control process guided by the mean and standard deviation values of the circuit performance characteristics. This provides two benefits. First, smaller expressions are obtained. Second, expression evaluation is faster: smaller number of operations - symbol products and term sums - are carried out since, at each Monte-Carlo run, only those symbols related to device mismatch are to be changed, while the rest remains constant. A comparison between the presented synthesis technique and other purely numerical and numerical/symbolic approaches is also given.
ACE16k: The third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs
A. Rodríguez-Vázquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro and S. Espejo-Meana
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 851-863, 2004
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Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm(2) and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3 x 3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.
Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
R. Carmona-Galán, F. Jiménez-Garrido, C.M. Domínguez-Mata, R. Domínguez-Castro, S. Espejo-Meana, I. Petras and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 913-925, 2004
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Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple, resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-mum CMOS technology.
Reaction-diffusion navigation robot control: From chemical to VLSI analogic processors
A. Adamatzky, P. Arena, A. Basile, R. Carmona-Galán, B. de Lacy-Costello, L. Fortuna, M. Frasca and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 926-938, 2004
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We introduce a new methodology and experimental implementations for real-time wave-based robot navigation in a complex, dynamically changing environment. The main idea behind the approach is to consider the robot arena as an excitable medium, in which moving objects-obstacles and the target-are represented by sites of autowave generation: the target generates attractive waves, while the obstacles repulsive ones. The moving robot detects traveling and colliding wave fronts and uses the information about dynamics of the autowaves to adapt its direction of collision-free motion toward the target. This approach allows us to achieve a highly adaptive robot behavior and thus an optimal path along which the robot reaches the target while avoiding obstacles. At the computational and experimental levels, we adopt principles of computation in reaction-diffusion (RD) nonlinear active media. Nonlinear media where autowaves are used for information processing purposes can therefore be considered as RD computing devices. In this paper, we design and experiment with three types of RD processors: experimental and computational Belousov-Zhabotinsky chemical processor, computational CNN processor, and experimental RD-CNN very large-scale integration chip-the complex analog and logic computing engine (CACE1k). We demonstrate how to experimentally implement robot navigation using space-time snapshots of active chemical medium and how to overcome low-speed limitation of this "wetware" implementation in CNN-based silicon processors.
Guest editorial for January 2004 special issue
A. Rodríguez-Vázquez, F. Medeiro and O. Feely
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 3, pp 437-439, 2004
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Abstract not available
Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
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We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.
Analysis of error mechanisms in switched-current sigma-delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 175-201, 2004
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This paper presents a systematic analysis of the major switched-current ( SI) errors and their influence on the performance degradation of SigmaDelta Modulators (SigmaDeltaMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass SigmaDeltaM (2nd-LPSigmaDeltaM) and a 4th-order BandPass SigmaDeltaM (4th-BPSigmaDeltaM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPSigmaDeltaMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI SigmaDeltaMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 mum CMOS SI 4th-BPSigmaDeltaM silicon prototype validate our approach.
Exploration of spatial-temporal dynamic phenomena in a 32 × 32-Cell stored program two-layer CNN universal machine chip prototype
I. Petrás, C. Rekeczky, T. Roska, R. Carmona, F. Jiménez-Garrido and A. Rodríguez-Vázquez
Journal Paper · Journal of Circuits, Systems and Computers, vol. 12, no. 6, pp 691-710, 2003
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This paper describes a full-custom mixed-signal chip that embeds digitally programmable analog parallel processing and distributed image memory on a common silicon substrate. The chip was designed and fabricated in a standard 0.5 μm CMOS technology and contains approximately 500 000 transistors. It consists of 1024 processing units arranged into a 32 × 32 grid. Each processing element contains two coupled CNN cores, thus, constituting two parallel layers of 32 × 32 nodes. The functional features of the chip are in accordance with the 2nd Order Complex Cell CNN-UM architecture. It is composed of two CNN layers with programmable inter- and intra-layer connections between cells. Other features are: cellular, spatial-invariant array architecture; randomly selectable memory of instructions; random storage and retrieval of intermediate images. The chip is capable of completing algorithmic image processing tasks controlled by the user-selected stored instructions. The internal analog circuitry is designed to operate with 7-bits equivalent accuracy. The physical implementation of a CNN containing second order cells allows real-time experiments of complex dynamics and active wave phenomena. Such well-known phenomena from the reaction-diffusion equations are traveling waves, autowaves, and spiral-waves. All of these active waves are demonstrated on-chip. Moreover this chip was specifically designed to be suitable for the computation of biologically inspired retina models. These computational experiments have been carried out in a developmental environment designed for testing and programming the analogic (analog-and-logic) programmable array processors.
ACE16k: a 128x128 focal plane analog processor with digital I/O
G.L. Cembrano, A. Rodríguez-Vázquez, S. Espejo Meana and R. Domínguez-Castro
Journal Paper · International Journal of Neural Systems, vol. 13, no. 6, pp 427-434, 2003
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This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.
An improved elementary processing unit for high-density CNN-based mixed-signal microprocessors for vision
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper · Journal of Circuits, Systems and Computers, vol. 12, no. 6, pp 675-690, 2003
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This paper presents the architecture of the (E) under bar lementary (P) under bar rocessing (U) under bar nit - EPU which has been employed to design a CNN-Based 128 x 128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3 x 3 convolution masks,1 or information propagative CNN templates.(2) Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128 x 128 EPUs and a completely digital interface, in a standard fully-digital 0.35 mum CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm(2) and 100 GOP/J.
A modem in CMOS technology for data communication on the low-voltage power line
O. Guerra, C.M. Domínguez-Matas, S. Escalera, J.M. García-González, G. Liñán, R. del Río, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Integration, the VLSI Journal, vol. 36, no. 4, pp 229-236, 2003
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This paper presents a CMOS 0.8 mum mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line. It includes all the analog circuitry needed for input interfacing and modulation/ demodulation (low-noise amplifier, PLL-based frequency synthesis, tunable filter banks, and decision circuitry), logic circuitry for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283muV(rms) (these are worst case values among 30 randomly-selected samples used as vehicles for detailed electrical characterization; most of the samples featured 200 muV(rms), sensitivity; bit error rate (BER) is below 0.5 x 10(-5)) at 10 kbps, and operates correctly in the whole industrial temperature range, from -45degreesC to 80degreesC, under 5% variations of the 5V supply voltage. This ASIC is now in commercial production. (C)2003 Published by Elsevier B.V.
A bio-inspired two-layer mixed-signal flexible programmable chip for early vision
R.C. Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, T. Roska, C. Rekeczky, I. Petras and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1313-1336, 2003
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A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the Visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 mum. CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.
Practical study of idle tones in 2nd-order bandpass Sigma Delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Microelectronics Journal, vol. 33, no. 11, pp 1005-1009, 2002
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This paper studies the tonal behaviour of the quantization noise in 2nd-order bandpass SigmaDelta modulators. Closed-form expressions for the frequency of the idle tones are derived for different locations of the signal centre frequency. The analytical results are validated through experimental measurements taken from a 0.8 mum CMOS prototype realized using fully differential switched-current circuits. (C) 2002 Elsevier Science Ltd. All rights reserved.
Architectural and basic circuit considerations for a flexible 128x128 mixed-signal SIMD vision chip
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 179-190, 2002
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From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 mum standard digital IP-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10-20 basic image processing tasks on each frame.
Toward visual microprocessors
T. Roska and A. Rodríguez-Vázquez
Journal Paper · Proceedings of the IEEE, vol. 90, no. 7, pp 1244-1257, 2002
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This paper outlines motivations and models underlying the design of visual microprocessors based on the cellular neural network universal machine. We also overview the state of the art regarding the realization of these microprocessors in the form of very large-scale integration chips. Examples corresponding to measurements realized on these chips are enclosed for illustration purposes.
Integrated chaos generators
M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Proceedings of the IEEE, vol. 90, no. 5, pp 747-767, 2002
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This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.
Introduction
T. Roska and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 30, no. 2-3, pp 87-88, 2002
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Abstract not available
ACE4k: An analog I/O 64 x 64 visual microprocessor chip with 7-bit analog accuracy
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 30, no. 2-3, pp 89-116, 2002
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This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 mum standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time ( < 300 ns for linear convolutions) and using a low power budget ( < 1.2 W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with > 7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templatesigma-either directly or through template decomposition. This means the 100% of the 3 x 3 linear templates reported in Roska et al. 1998, [1]. Copyright (C) 2002 John Wiley Sons, Ltd.
A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips
P. Földesy and A. Rodriguez Vazquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 30, no. 2-3, pp 139-163, 2002
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This paper describes procedures to build custom-tailored behavioural models of cellular neural networks (CNNs), and acompanion tool to run these models. The main property of the CNNs is the emerging behaviour, i.e. new phenomena arise from the interactions of thousands of identical cells. The existence of these phenomena need is to be checked during the design phase, which requires a full network simulation and therefore constitutes a very time-consuming step of circuit verification. To solve this task as a modelling problem, we introduce a new behavioural model optimization technique. Starting from a user-defined set of block models, the proposed framework produces an optimized selection which is used to build up a full-chip model. The optimization goal is the minimization of the simulation CPU time and the maximization of the time domain precision. A dedicated environment has been developed for efficient numerical simulations this environment is briefly described in the paper. Two case studies are also presented to demonstrate the effectivity of the technique.
Approximate symbolic analysis of hierarchically decomposed analog circuits
O. Guerra, E. Roca, F.V. Fernandez and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp 131-145, 2002
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This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.
Congresos
A self-powered asynchronous image sensor with independent in-pixel harvesting and sensing operations
R. Gomez-Merchan, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2023
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A self-powered asynchronous sensor with a novel pixel architecture is presented. Pixels are autonomous and can harvest or sense energy independently. During the image acquisition, pixels toggle to a harvesting operation mode once they have sensed their local illumination level. With the proposed pixel architecture, most illuminated pixels provide an early contribution to power the sensor, while low-illuminated ones spend more time sensing their local illumination. Thus, the equivalent frame rate is higher than the one offered by conventional self-powered sensors that harvest and sense illumination in independent phases. The proposed sensor uses a Time-to-First-Spike readout that allows trading between image quality and data and bandwidth consumption. The device has HDR operation with a dynamic range of 80 dB. Pixel power consumption is only 70 pW. The article describes the sensors and pixel’s architectures in detail. Experimental results are provided and discussed. Sensor specifications are benchmarked against the art.
Experimental Validation of a High-Voltage Compliant Neural Stimulator Implemented in a Standard 1.8V/3.3V CMOS Process
D. Palomeque-Mangut, A. Rodríguez-Vázquez and M Delgado-Restituto
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2022
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This paper describes a neural stimulator with 4 × VDD compliance voltage, delivering up to 2.08 mA, and implemented in a standard 180nm 1.8V/3.3V CMOS Process. The wide range of stimulation currents and high compliance voltage makes it suitable for stimulation applications both in rodents and mammals. Besides, it can be configured both as electrical and optical stimulator. Stacked transistor cells with dynamic gate biasing have been used for withstanding voltages well above the nominal supply. The system has been fabricated, occupying an active area of 2.34mm2. The circuit has been experimentally tested by connecting it to a custom μelectrode array which was immersed into a phosphate-buffered saline solution.
PixiStamp: A tool to acquire, process, and sequence AER data from event-driven systems
R. de la Rosa-Vidal, R. Gomez-Merchan, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2022
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We present a new tool, PixiStamp, to readout, process, and sequence data of event-driven systems that exchange data using the Address Event Representation (AER) protocol. PixiStamp is a compact acquisition board that can be easily attached to other devices. Over other existing solutions, it has enhanced hardware processing capabilities to process AER data and generate control signals after data processing, making possible a closed-loop device control. The article describes in detail the system architecture, its mechanical design, and its main features.
On the implementation of in-pixel controlled diodes with sensing and energy harvesting capabilities
R. Gomez-Merchan, R. de la Rosa-Vidal, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2022
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Energy harvesting plays a crucial role in low-power systems and Internet-of-Things (IoT) sensing nodes. Measuring the illumination level of the scene is desired in such applications. Few studies have explored the possibility of designing image sensors that use photodiodes to harvest energy from the scene to reduce consumption or even achieve a self-powered operation using frame-based approaches. This work aims to validate the switching capabilities of photodiodes independently within a photodiode array. While most studies focus on alternating the harvesting and sensing operation in two different phases, in this approach a fraction of the photodiodes are connected to a global node to harvest energy, while the rest are sensing. This configuration qualifies to design asynchronous imagers and optimize the harvesting operation. The preliminary experimental results reported in this publication emphasize the validity of this asynchronous switching in photodiode arrays.
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils
D. Palomeque-Mangut, A. Schmid, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2022
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This paper proposes a system to transfer both mWpower and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.
On the Application of Quanta Imaging Acquisition to Spiking Luminance Sensors
R.J. Méndez-Romero, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2022
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Spiking luminance asynchronous sensors are image sensors whose pixels spike asynchronously and autonomously with a frequency proportional to illumination. They can render images with low latency, high dynamic range, and low power consumption. However, one of their drawbacks is the operation under high illumination or with large pixel arrays that can easily saturate their asynchronous readout logic. In this article, the novel quanta imaging acquisition technique is evaluated to alleviate this limitation. Simulation and experimental results demonstrate that the technique is easy to implement. It also reduces the data throughput, keeping acceptable image quality.
A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process
D. Palomeque-Mangut, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2022
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A high-voltage (HV) floating level shifter which slides digital signals by varying the low supply rail from ground to VSSH while preserving the input signal swing is proposed. The cell is based on a periodically-refreshed charge pump circuit and it is suitable for non-HV CMOS processes. Input signals can be non-periodic. The circuit has been designed and implemented in a standard 180nm 1.8V/3.3V CMOS node, occupying 0.02mm2. Post-layout simulations show that VSSH voltage can safely range from 0.5V to 9.5V. The delay response of the circuit is 1.9 ns and it consumes 13.9 μW.
Design of Readout Channels for Direct-ToF LiDAR
M. Parsakordasiabi, A. Rodríguez-Vázquez and R. Carmona-Galán
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2021
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Direct-time-of-flight (d-ToF) readout channels are required to be precise, high speed, and linear while preserving low resources for multi-channel applications. Although meeting these requirements seems to be difficult, they are highly demanded in many applications like light detection and ranging (LiDAR) sensors. This thesis project is dedicated to the design of a high-linearity high-measurement throughput low-resources FPGA-based time-to-digital converters (TDCs). We are working on the reduction of the dead-time by using a toggling input stage and a dual-mode counter-based encoder. In addition, the linearity is improved by using a dual-mode bin-width calibrator and a robust encoder.
A high-speed low-power sun sensor with solar cells and continuous operation
R. Gomez-Merchan, M. López-Carmona, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · European Solid-State Circuits Conference ESSCIRC 2021
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A novel sun sensor concept is presented. Photodiodes operating as solar cells with continuous operation and dedicated logic to calculate the centroid position are integrated to achieve lower latency and energy consumption. The output data flow is remarkably reduced because the centroid of the illuminated pixels is the only sensor output data. It overcomes conventional digital sun sensors based on Active Pixel Sensor (APS) pixels and Address Event Representation (AER) in terms of latency and power consumption. Its latency is in the order of microseconds with an average power consumption lower than 100 uW. Experimental results are provided and benchmarked.
A Novel Approach for Measurement Throughput Maximization in FPGA-based TDCs
M. Parsakordasiabi, I. Vornicu, A. Rodríguez-Vázquez and R. Carmona-Galán
Conference · International Conference on Event-Based Control, Communication and Signal Processing EBCCSP 2021
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This paper presents a new approach for dead-time minimization while preserving low resource usage and high resolution in FPGA-based time-to-digital (TDC) converters. The proposed TDC architecture can be employed in applications in which many events need to be detected in a short time, such as time-of-flight positron emission tomography (ToF-PET) applications. The presented architecture consists of a toggling input stage, a tapped delay line (TDL), a dual-mode counter-based encoder, a coarse counter, and a bin width calibration stage. The minimum dead-time of TDL TDCs is two clock cycles. The proposed architecture reduced dead-time to one clock cycle. The measurement results of the proposed low-resources TDC in an Artix-7 FPGA show [-0.80, 1.34] LSB differential nonlinearity (DNL) and [-0.73, 1.97] LSB integral non-linearity (INL). The measured LSB size and single-shot precision (SSP) are 22.1 ps and 28.43 ps, respectively.
Spatial Encoding Techniques in Time-Multiplexed Neural Recording Front-Ends
N. Pérez-Prieto, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2021
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This paper reviews two spatial encoding techniques for time-multiplexed recording front-ends. These techniques use bipolar and monopolar recordings, respectively, and are aimed to compress neural data taking advantage of the large spatial correlation of LFPs/ECoGs measured from nearby electrodes. The pros and cons of both architectures are analyzed and demonstrated with experimental results from a 32-channel time-multiplexed spatially-encoded neural front-end designed in 0.18 µm technology.
Photon-Detection Timing-Jitter Model in Verilog-A
J.M. López-Martínez, R. Carmona-Galán and A. Rodríguez-Váquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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Single-photon avalanche diodes can be employed to register the arrival of an individual photon. They are biased beyond breakdown voltage, and thus the electron-hole pairs generated by any incident photon is accelerated by the strong electric field triggering an avalanche current. In recent years, there have been attempts to model its characteristics in Verilog-A HDL. However, none of them have modelled its photon-detection timing jitter. This paper explains the mechanism of avalanche triggering and proposes a first approach to model it in Verilog-A. Comparison with experimental data and data reported in literature validates the model.
Limitation of SPADs quantum efficiency due to the dopants concentration gradient
J.M. López-Martínez, R. Carmona-Galán and A. Rodríguez-Váquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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Single-photon avalanche diodes are highly sensitive devices capable of registering the arrival of an individual photon. They are biased beyond breakdown voltage, and thus the electron-hole pairs generated by any incident photon is accelerated by the strong electric field triggering an avalanche current. This paper examines the role of the dopants concentration gradient in the gathering of photons in these devices, and how it can be engineered to maximize quantum efficiency and explain his role to minimize undesirable effects like crosstalk.
Cellular-Neural-Network Focal-Plane Processor as Pre-Processor for ConvNet Inference
L.C. Gontard, R. Carmona-Galán and A. Rodríguez-Váquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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Cellular Neural Networks (CNN) can be embodied in the form of a focal-plane image processor. They represent a computing paradigm with evident advantages in terms of energy and resources. Their operation relies in the strong parallelization of the processing chain thanks to a distributed allocation of computing resources. In this way, image sensing and ultra-fast processing can be embedded in a single chip. This makes them good candidates for portable and/or distributed applications in fields like autonomous robots or smart cities. With the irruption of visual features learning through convolutional neural networks (ConvNets), several works attempt to implement this functionality within the CNN framework. In this paper we carry out some experiments on the implementation of ConvNets with CNN hardware in the form of a focal-plane image processor. It is shown that ultra-fast inference can be implemented, using as an example a LeNet-based ConvNet architecture.
VersaTile Convolutional Neural Network Mapping on FPGAs
A. Muñío-Gracia, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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Convolutional Neural Networks (ConvNets) are directed acyclic graphs with node transitions determined by a set of configuration parameters. In this paper, we describe a dynamically configurable hardware architecture that enables data allocation strategy adjustment according to ConvNets layer characteristics. The proposed flexible scheduling solution allows the accelerator design to be portable across various scenarios of computation and memory resources availability. For instance, FPGA block-RAM resources can be properly balanced for optimization of data distribution and minimization of off-chip memory accesses. We explore the selection of tailored scheduling policies that translate into efficient on-chip data reuse and hence lower energy consumption. The system can autonomously adapt its behavior with no need of platform reconfiguration nor user supervision. Experimental results are presented and compared with state-of-the-art accelerators.
Sun tracker sensor for attitude control of space navigation
systems
A. de la Calle-Martos, R. Gómez-Merchán, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2020
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We report a sun tracker sensor lor attitude conlrol 01 space navigation systems. The sensor exploits the concept 01 asynchronous operation previously devised by the authors lor those de vices. Asynchronous luminance sensors optimize sun trackers operation because only illuminated pixels are readout and can transmit data. This approach outperlorms classic Irame-based sun trackers in terms 01 bandwidth consumption, latency, and power consumption. The new sensor under study has been optimized lor operation and interaclion with other attitude control systems when it is embarked. The sensor power consumplion is quite reduced. To save power, its pixels enler automatically in standby mode after gauging illuminalion levels. The device operates with only 0.45V. The pixel matrix has been devised to optionally be direclly powered by energy harvesting syslems based on photovoltaic dio des connected lo a storage capacitor wilhout a DC-DC con verter.
Demo: A system for image acquisition and processing operating in the visible and the IR bands
J.A. Lenero-Bardallo, J. Bernabeu-Wittel, J. Ceballos-Caceres and A. Rodriguez-Vazquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2020
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This demo displays an autonomous image acquisition and processing system that operates simultaneously with two image sensors either in the visible and the Long Wave Infrared Band (LWIR), inside the Infrared (IR) band. The entire system is controlled a Raspberry Pi board that allows to easily program image processing algorithms to process the images acquired with each sensor. It is a competitive alternative to conventional commercial closed systems with infrared cameras. The proposed imaging system can be easily adapted to different operation scenarios by adding new peripherals, sensors and full custom image processing algorithms.
Demo: CNN Performance Prediction on a CPU-based Edge Platform
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez Vázquez
Conference · International Conference on Sustainable Development in Civil Engineering ICSDC 2019
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The implementation of algorithms based on Dee p Learning at edge visual systems is currently a challenge. In addition to accuracy, the network architecture also has an impact on inference performance in terms of throughput and power consumption. This demo showcases per layer inference performance of various convolut ional neural networks running at a low cost edge platform . Furthermore, a n empirical model is applied to predict processing time and power consumption prior to actually running the networks A comparison between the prediction from our model and the actual inference performance is displayed in real time.
PhD Forum: A survey on FPGA-based high-resolution TDCs
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICSDC 2019
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Time-to-digital converters based on Nutt method are especially suitable for FPGA implementation. They are able to provide high resolution, range and linearity with low resources usage. The core of this architecture consist in a coarse counter for long range, a fine time interpolator for high resolution and real-time calibration for high linearity. This paper reviews different time interpolation and real-time calibration techniques. Moreover, a comparison of state-of-the-art FPGA-based TDCs is presented as well.
PhD Forum: Impact of CNNs Pooling Layer Implementation on FPGAs Accelerator Design
A. Muñío-Gracia, J. Fernández-Berni, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICSDC 2019
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Convolutional Neural Networks have demonstrated their competence in extracting information from data, especially in the field of computer vision. Their computational complexity prompts for hardware acceleration. The challenge in the design of hardware accelerators for CNNs is providing a sustained throughput with low power consumption, for what FPGAs have captured community attention. In CNNs pooling layers are introduced to reduce model spatial dimensions. This work explores the influence of pooling layers modification in some state-of-the-art CNNs, namely AlexNet and SqueezeNet. The objective is to optimize hardware resources utilization without negative impact on inference accuracy.
A High TCMRR, Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation
J.L. Valtierra, R. Fiorelli, N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2019
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This paper describes a multichannel bidirectional front-end for true closed-loop neuromodulation. Stimulation artefacts are reduced via a 4-channel H-bridge current source sharing stimulators to minimize residual charge drops in the electrodes. The 4-channel sensing front-end is capable of multichannel sensing in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR drop due to electrode mismatch. Experimental verification of a prototype fabricated in 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 μW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.
A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression
N. Pérez-Prieto, R. Fiorelli, J.L. Valtierra, P. Pérez-García, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2019
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This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. In order to reduce interface area, a 32-channel multiplexer is implemented on circuit input. Furthermore, a spatial delta encoding is proposed to compress the signal range. A differential artifact compression algorithm is implemented to avoid saturation in the signal path, thus enabling reconstruct or suppressing artifacts in digital domain. The proposed design has been implemented using 0.18 μm TSMC technology. Experimental results shows a power consumption per channel of 1.0 μW, an input referred noise of 1.1 μVrms regarding the bandwidth of interest and a dynamic range of 91 dB.
Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology
I. Vornicu, F. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · European Solid-State Device Research Conference ESSDERC 2019
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Photon detection at longer wavelengths is much desired for LiDAR applications. Silicon photodiodes with deeper junctions and larger multiplication regions are more sensitive to near-IR photons. This paper presents the complete electro-optical characterization of a P-well/Deep N-well single photon avalanche diode integrated in 110nm CIS technology. Devices with various sizes, shapes and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is of 18V. The proposed structure has 0.4Hz/um2 dark count rate, 0.5% afterpulsing, 188ps FWHM (total) jitter and around 10% photon detection probability at 850nm wavelength. All figures have been measured at 3V excess voltage.
Evaluation of Architectures for FPGA-Implementation of High-Resolution TDCs
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2019
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Time-to-digital converters (TDCs) are a central component in systems based on time-delay assessment. The principal characteristics to be sought for in a TDC are high resolution, long time range, linearity and low power consumption. Besides, field-programmable gate arrays (FPGAs) represent an interesting option to explore fully-digital TDC architectures, because of their flexibility, shorter development time and lower implementation cost than ASICs. They are reconfigurable and usually built on the finest silicon technologies. The purpose of this work is to identify the different architectures that lead to high-resolution TDCs on FPGA, and to compare them in terms of the appropriate figures of merit. The most extended method to cover a long time interval while preserving a high time resolution is to combine a coarse counter with a fine time interpolator. Two techniques have been widely used to implement the interpolator, namely a tapped delay line (TDL) and a multiple-phase clock interpolator. Exploiting fast carry chains present in most modern FPGAs, sub-clock-period resolution have been achieved, down to tens of picoseconds. Other important aspects of the TDC design are the thermometer-to-binary encoder, the minimization of the clock skew, the analysis of the influence of voltage and temperature changes and bin-width calibration. Accordingly, we report an analysis of the different TDC architectures on FPGA based on their performance characteristics.
Towards a Simplified Procedure for CNN Performance Prediction on Embedded Platforms
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2019
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Vision is arguably the technical field benefiting the most from the renaissance of artificial intelligence in the last few years. In particular, the convergence of massive datasets for training, boosted computational power, and enhanced machine learning techniques has given rise to highly accurate vision algorithms -even outperforming humans in certain tasks- based on convolutional neural networks (CNNs). The potential of these algorithms has attracted attention from many parties, both in academia and industry, spurring the development of a myriad of hardware platforms and software frameworks. The challenge now is how to efficiently leverage and integrate this variety of components in practical realizations, taking also into account that CNN models keep evolving at a rapid pace. With this scenario in mind, we have been working on a simplified procedure to predict the performance of CNNs running on embedded platforms in terms of throughput and power consumption. The objective is to facilitate the evaluation of the aforementioned components and CNN models prior to actually implementing them, thereby speeding up the deployment of optimal solutions. In this talk, we will describe key aspects of the proposed procedure. Specifically, we will elaborate on SweepNet, a deep neural network tailored for meaningful per-layer characterization. The performance models extracted from SweepNet for a hardware platform allow to accurately predict layer by layer the execution time and energy consumption of any other CNN running on that platform.
On the Balanced Allocation of Convolutional Neural Network Models on FPGAs
A. Muñío-Gracia, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2019
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Deep Learning (DL) algorithms have demonstrated their competence in accurately extracting information from data, especially in the field of computer vision. DL has emerged as an end-to-end approach based on learned multi-level scene representations. A number of open-source frameworks have been created to describe convolutional neural network (CNN) models -a class of the deep neural networks (DNNs) that support DL. Their computational complexity prompts for hardware acceleration. The challenge in the design of hardware accelerators for CNNs is providing a sustained throughput with low power consumption. In order to test our architectural proposals, we will be employing FPGAs. They are reconfigurable, efficient, and have adjustable precision. FPGAs permit architectural exploration with shorter development time and lower cost than ASICs. This work introduces an scalable, frameworkagnostic, architecture whose behavior self-adapts to the selected CNN configuration. A design space analysis is performed for some state-of-the-art CNNs, namely VGG-16, Tiny DarkNet, and SqueezeNet. The objective is a balanced allocation of resources. For this, tiling parameterization will be optimized attending to decisive performance criteria such as the number of memory accesses, data movement policy and throughput.
On the Correlation of CNN Performance and Hardware Metrics for Visual Inference on a Low-Cost CPU-based Platform
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Conference on Systems, Signals and Image Processing IWSSIP 2019
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While providing the same functionality, the various Deep Learning software frameworks available these days do not provide similar performance when running the same network model on a particular hardware platform. On the contrary, we show that the different coding techniques and underlying acceleration libraries have a great impact on the instantaneous throughput and CPU utilization when carrying out the same inference with Caffe, OpenCV, TensorFlow and Caffe2 on an ARM Cortex-A53 multi-core processor. Direct modelling of this dissimilar performance is not practical, mainly because of the complexity and rapid evolution of the toolchains. Alternatively, we examine how the hardware resources are distinctly exploited by the frameworks. We demonstrate that there is a strong correlation between inference performance - including power consumption - and critical parameters associated with memory usage and instruction flow control. This identified correlation is a preliminary step for the development of a simple empirical model. The objective is to facilitate selection and further performance tuning among the ever-growing zoo of deep neural networks and frameworks, as well as the exploration of new network architectures.
A sub-μVRMS chopper front-end for ECOG recording
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
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This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μVrms, with a noise floor below 50 nV/Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.
Artifact-aware analogue/mixed-signal front-ends for neural recording applications
N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
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This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog front-ends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog front-end and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.
TOF estimation based on compressed real-time histogram builder for SPAD image sensors
I. Vornicu, A. Darie, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
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This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation algorithms rely on complete ToF histograms. The next generation of high speed dToF-CIS is expected to have wide dynamic range and high depth resolution. Applications such as 3D imaging based on dToF-CISs require pixel-level ToF histograms which have to be stored by huge fully-random access memory (RAM) modules. The proposed shifted inter-frame histogram (SiFH) algorithm has the same accuracy but requires a memory footprint 128 times smaller than the conventional algorithm. Thus a much larger number of pixels can be resolved using limited block RAM resources of FPGAs. Moreover the overall frame rate is also remarkably improved compared to the scanning method. The proof of concept of the SiFH algorithm on 15 bits has been implemented on Spartan-3E. An automated testbench was developed to confirm that no ambiguity errors occur along the entire dynamic range.
A Sub- µW Reconfigurable Front-End for Invasive Neural Recording
J.L. Valtierra, R. Fiorelli, M. Delgado-Restituto and A. Rodriguez-Vazquez
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2019
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This paper presents a sub-microwatt ac-coupled neural amplifier for the purpose of neural signal sensing. A proposed reconfigurable topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180nm CMOS process draws 803nW from a 1V source. The measured input-referred spot-noise at 150Hz is 130nV / Hz while the integrated noise in the 200Hz-5kHz band is 3.6µV rms.
On the implementation of asynchronous sun sensors
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2019
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Abstract not avaliable
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation
J.M. López-Martínez, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2018
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Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new approach to model them in Verilog-A HDL with the help of a powerful tool: TCAD simulation. Besides, to the best of our knowledge, this is first model to incorporate a trap-assisted tunneling mechanism, a cross-section temperature dependence of the traps, and the self-heating effect. Comparison with experimental data establishes the validity of the model.
Highly scalable real time epilepsy diagnosis architecture via phase correlation and functional brain maps
J.B. Romaine, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2018
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The complexity of biomedical neural processing is evident, with vast amounts of data needing to be handled and processed in order to reveal possible biomarkers which may lead to the early diagnosis of certain neurological disorders. One disorder in particular is epilepsy, which is one of the most common neurological disorder in the world today.Our proposed solution is a highly efficient, scalable and low powered device for the diagnosis and verification of epilepsy via the identification of changes in synchronicity between interictal neural signal segments.
1D Cellular Automata for Pulse Width Modulated Compressive Sampling CMOS Image Sensors
M. Trevisi, R. Carmona-Galan and A. Rodriguez-Vazquez
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2018
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Compressive sensing (CS) is an alternative to the Shannon limit when the signal to be acquired is known to be sparse or compressible in some domain. Since compressed samples are non-hierarchical packages of information, this acquisition technique can be employed to overcome channel losses and restricted data rates. The quality of the compressed samples that a sensor can deliver is affected by the measurement matrix used to collect them. Measurement matrices usually employed in CS image sensors are recursive random-like binary matrices obtained using pseudo-random number generators (PRNG). In this paper we analyse the performance of these PRNGs in order to understand how their non-idealities affect the quality of the compressed samples. We present the architecture of a CMOS image sensor that uses class-III elementary cellular automata (ECA) and pixel pulse width modulation (PWM) to generate onchip a measurement matrix and high the quality compressed samples.
Gaussian Pyramid: Comparative Analysis of Hardware Architectures
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
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A comparison of architectures for hardware implementation of Gaussian image pyramids is addressed. Architectures consisting of a conventional sensor followed by digital processors are compared to architectures employing per-pixel embedded pre-processing structures. The later is potentially advantageous for enhancing throughput and reducing energy consumption, important features in the IoT context. These advantages are quantified considering different numbers of digital processors and ADCs, and different ADCs types. Results show that the advantages of pre-processing sensors are not granted by default, requiring proper architectural design. The methodology presented for comparing focal-plane and digital approaches allows for the assessment of focal-plane processing advantages.
Results of 'iCaVeats', a project on the integration of architectures and components for embedded vision
R. Carmona-Galán, J. Fernández-Berni, A. Rodríguez-Vázquez, P. López-Martínez, V.M. Brea-Sánchez, D. Cabello-Ferrer, G. Domenech-Asensi, R. Ruiz-Merino and J. Zapata-Pérez
Conference · International Conference on Distributed Smart Cameras ICDSC 2018
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iCaveats is a Project on the integration of components and architectures for embedded vision in transport and security applications. A compact and efficient implementation of autonomous vision systems is difficult to be accomplished by using the conventional image processing chain. In this project we have targeted alternative approaches, that exploit the inherent parallelism in the visual stimulus, and hierarchical multilevel optimization. A set of demos showcase the advances at sensor level, in adapted architectures for signal processing and in power management and energy harvesting.
On the characterization of light sources irradiation profiles with an HDR image sensor
J.A. Leñero-Bardallo, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2018
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We demonstrate how light emissions of very bright light sources can be rendered with an HDR image sensor with linear operation. We showcase the device usefulness to study transient variations of very high illumination levels and to determine the irradiance profile of light sources. The sensor can track transient illumination changes at video rates, preserving details of darker regions within the visual scene.
CMOS-SPAD camera prototype for single-sensor 2D/3D imaging
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2018
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One of the research lines explored in project 'iCaveats' has been the combined capture of 2D and 3D visual information. With the objective of power-efficient feature learning/extraction, combined 2D/3D imaging is a useful tool to work on a lightweight but rich description of the scene. Single-sensor capture of both modalities is a potential improvement in cost and efficiency. In this demo, we present the performance and features of a CMOS-SPAD camera prototype that realizes photon counting and direct time-of-flight (d-ToF). The central elements of the camera module are a 64x64 SPAD imager and a FPGA board for real time histograming and image reconstruction at 1kfps.
On-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camera
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galan and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2018
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This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image recognition on deep neural networks. Both the hardware configuration and the network model can be changed any time on the fly. Up to 24 hardware-model combinations are possible, enabling dynamic reconfiguration according to prescribed application requirements.
Optimum Network/Framework Selection from High-Level Specifications in Embedded Deep Learning Vision Applications
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Advanced Concepts for Intelligent Vision Systems ACIVS 2018
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This paper benchmarks 16 combinations of popular Deep Neural Networks and Deep Learning frameworks on an embedded platform. A Figure of Merit based on high-level specifications is introduced. By sweeping the relative weight of accuracy, throughput and power consumption on global performance, we demonstrate that only a reduced set of the analyzed combinations must actually be considered for real deployment. We also report the optimum network/framework selection for all possible application scenarios defined in those terms, i.e. weighted balance of the aforementioned parameters. Our approach can be extended to other networks, frameworks and performance parameters, thus supporting system-level design decisions in the ever-changing ecosystem of Deep Learning technology.
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
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Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-todigital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper we are covering the modeling, design and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64×64-pixel array. It has been fabricated in a 0.18μm standard CMOS technology. Occupation area is 28×29μm2 and power consumption is 1.17mW at 850MHz. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of -102dBc/Hz at 2MHz offset frequency from 850MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147ps with a RMS DNL/ INL of 0.13/ 1.7LSB.
Live Demonstration: Low-Power Low-Cost Cyber-Physical System for Bird Monitoring
A. García-Rodríguez, R. Rodríguez-Sakamoto, J. Fernández-Berni, R. del Río, J. Marín, M. Baena, J. Bustamante, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
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This live demonstration showcases a cyber-physical system tailored for inexpensive remote bird monitoring. A comprehensive analysis of the application requirements along with a tight system integration have given rise to a smart autonomous nest-box ready for deployment. This nest-box includes radiofrequency identification (RFID), a weighing scale, two temperature sensors, passive infrared devices (PIR), massive data storage and internet connection via mobile infrastructure. It is powered through a solar panel. The bill of materials has been diminished 77% with respect to the previous version of the nest-box whereas the power consumption has been reduced 84%.
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodríguez-Pérez, A. Darie, A. Rodríguez-Vázquez, C. Soto-Sánchez and E. Fernández-Jover
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
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This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an autocalibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data stream coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.
Color Tone-Mapping Circuit for a Focal-Plane Implementation
G.M.S. Nunes, F.D.V.R. Oliveira, J.G. Gomes, A. Petraglia, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
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In this article, we present a review of the driving principles and parameters of a previously reported focal-plane tone-mapping operator. We then extend it in order to include color information processing. The signal processing operations required for handling color images are white balance and demosaicing. Neither white balance nor demosaicing are carried out in the focal plane, in order to avoid increasing circuit size and complexity. Since, in this case, white balance is carried out after tone mapping, multiplication of red and blue channels by constant gains may lead to wrong color results. An alternative approach is proposed, in which different gains are assigned for every red and blue pixel of the matrix. Because of the introduction of color, a modification in the original circuit is proposed, which affects the integration time of red and blue pixels. This modification leads to a reduction in the number of photodiodes required in the pixel array, and hence to a reduction of the sensing circuit area. The results produced by the operator are compared to those obtained from two other digital tone-mapping operators.
Concurrent focal-plane generation of compressed samples from time-encoded pixel values
M. Trevisi, H.C. Bandala, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Design Automation and Test in Europe DATE 2018
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Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity of natural images. This principle can be employed to deliver images over a network under a restricted data rate and still receive enough meaningful information. An efficient implementation of this principle lies in the generation of the compressed samples right at the imager. Otherwise, i. e. digitizing the complete image and then composing the compressed samples in the digital plane, the required memory and processing resources can seriously compromise the budget of an autonomous camera node. In this paper we present the design of a pixel architecture that encodes light intensity into time, followed by a global strategy to pseudo-randomly combine pixel values and generate, on-chip and on-line, the compressed samples.
Performance Analysis of Real-Time DNN Inference on Raspberry Pi
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · SPIE Real-Time Image and Video Processing 2018
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Deep Neural Networks (DNNs) have emerged as the reference processing architecture for the implementation
of multiple computer vision tasks. They achieve much higher accuracy than traditional algorithms based on
shallow learning. However, it comes at the cost of a substantial increase of computational resources. This
constitutes a challenge for embedded vision systems performing edge inference as opposed to cloud processing.
In such a demanding scenario, several open-source frameworks have been developed, e.g. Ca e, OpenCV,
TensorFlow, Theano, Torch or MXNet. All of these tools enable the deployment of various state-of-the-art
DNN models for inference, though each one relies on particular optimization libraries and techniques resulting
in di erent performance behavior. In this paper, we present a comparative study of some of these frameworks
in terms of power consumption, throughput and precision for some of the most popular Convolutional Neural
Networks (CNN) models. The benchmarking system is Raspberry Pi 3 Model B, a low-cost embedded platform
with limited resources. We highlight the advantages and limitations associated with the practical use of the
analyzed frameworks. Some guidelines are provided for suitable selection of a speci c tool according to prescribed
application requirements.
A 5-Megapixel 100-Frames-per-second 0.5erms Low Noise CMOS Image Sensor with Column-Parallel Two-Stage Oversampled Analog-to-Digital Converter
J.A. Segovia, F. Medeiro, A. González, A. Villegas and A. Rodríguez-Vázquez
Conference · International Image Sensor Workshop, 2017
resumen
Abstract not avaliable
Gaussian Pyramid: Comparative Analysis of Hardware Architectures
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2017
resumen
Abstract not avaliable
Compressed Sampling CMOS Imager based on Asynchronous Random Pixel Contributions
M. Trevisi, H.C. Bandala-Hernandez, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2017
resumen
Abstract not avaliable
Smart single-photon detectors in CMOS technology
A. Rodriguez-Vazquez
Conference · SPIE Optics + Photonics 2017
resumen
Abstract not avaliable
Characterization of Electrical Crosstalk in 4T-APS Arrays using TCAD Simulations
J.M. López-Martínez, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2017
resumen
TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the crosstalk between pixels through the study of the electric field
distribution. The image sensor consists on a linear array of five pinned photodiodes (PPD) with their transmission gates, floating diffusion and reset transistors. The effect of the variations of the thickness of the epitaxial layer has been addressed as well. In fact, the depth of the boundary of the epitaxial layer affects quantum efficiency (QE) so a correlation with crosstalk has been identified.
Design of a Compact and Low-Power TDC for an Array of SiPM´s in 110nm CIS Technology
F.N. Bandi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2017
resumen
Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their -to name a few interesting
Properties- compactness, lower bias voltage, tolerance to magnetic fields and finer spatial resolution. SiPMs can also be built in CMOS technology. This allows the incorporation of active
quenching and recharge schemes at cell level and processing circuitry at pixel level. One of the elements that can lead to finer temporal resolutions is the time-to-digital converter (TDC).
In this paper we describe the architecture of a compact TDC to be included at each pixel of an array of SiPMs. It is compact and consumes low power. It is based on a voltage controlled oscillator that generates multiple internal phases that are interpolated to provide time resolution below the time delay of a single gate. Simulation results of a 11b TDC based on a 4-stage VCRO in 110nm CIS technology yield a time resolution of 80.0ps, a DNL of ±0.28 LSB, a INL ±0.52 LSB, and a power consumption of 850μW.
Compressive Image Sensor Architecture with On-Chip Measurement Matrix Generation
M. Trevisi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2017
resumen
A CMOS image sensor architecture that uses a cellular automaton for the pseudo-random compressive sampling matrix generation is presented. The image sensor employs inpixel pulse-frequency modulation and column wise pulse counters to produce compressed samples. A common problem of compressive sampling applied to image sensors is that the size of a full-frame compressive strategy is too large to be stored in an on-chip memory. Since this matrix has to be transmitted to or from the reconstruction system its size would also prevent practical applications. A full-frame compressive strategy generated using a 1-D cellular automaton showing a class III behavior neither needs a storage memory nor needs to be continuously transmitted. In-pixel pulse frequency modulation and up-down counters allow the generation of differential compressed samples directly in the digital domain where it is easier to improve the required dynamic range. These solutions combined together improve the accuracy of the compressed samples thus improving the performance of any generic reconstruction algorithm.
TCAD Simulation of Electrical Crosstalk in 4T-Active Pixel Sensors
J.M. López-Martínez, R. Carmona-Galán, J. Fernández-Berni and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2017
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CMOS image sensors (CIS) are widely used nowadays in consumer electronics as well as in high-end applications. This is mainly due to their advantages regarding low dark current and low noise characteristics of the pinned photodiode (PPD). Much effort has been put into better understanding key electrical properties of PPDs, like full well capacity, photodiode´s capacitance or pinning voltage. Another important source of sensitivity degradation is crosstalk (CTK). It has been assessed for CCDs and some CMOS devices. However, addressing CTK in CMOS 4T-APS pixels at the design phase is not easy, mainly due to the unavailability of CIS technology parameters.an additional problem is the computational cost of TCAD simulation; e.g., a five pixel linear array like the one shown in Fig. 1, already introduce long periods of computing due to the complexity of the structure. Crosstalk occurs when the charge generated by photon incident on a pixel are finally sensed by a neighboring pixel. CTK degrades performance, cutting down spatial resolution, reducing the overall sensitivity, degrading color separation, and increasing image noise. Crosstalk is defined as the percentage of the total charge generated by incident light that is diverted to non-illuminated pixels in the neighborhood. There are two components in CTK. Optical crosstalk is related to illumination, reflection, refraction and scattering of photons in the different layers of the material that cover the photodiode. This generates stray photons that are absorbed in the neighborhood. The second component is electrical, and it involves the diffusion of photo-generated carriers between adjacent devices. The characterization of electrical CTK in 4T-APS can be achieved using TCAD tools. Particularly, the relation between CKT and quantum efficiency (QE) can be explored and linked to the thickness of the epitaxial layer.
On the design of sun sensors with event-based operation
J.A. Leñero-Bardallo, L. Farian, J.M. Guerrero-Rodríguez, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2017
resumen
Abstract not avaliable
Real-time phase correlation based integrated system for seizure detection
J.B. Romaine, M. Delgado-Restituto, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · Bio-MEMS and Medical Microdevices III Conference 2017
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This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.
A sun sensor implemented with an asynchronous luminance vision sensor
J.A. Leñero-Bardallo, L. Farian, J.M. Guerrero-Rodríguez, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · European Solid-State Circuits Conference ESSCIRC 2017
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A sun sensor implemented with a spiking pixel matrix is reported. It is the very first sun sensor based on an asynchronous event-based pixel array. A paradigm associted to classic digital sun sensors is solved with this approach. Only the pixels illuminated by the sun light are readout. Hence, the output data flow is quite reduced. The computational load to resolve the sun position is quite low, comparing to prior sensors. Sensor's latency is in the order of milliseconds. The advantages over implementations with APS pixels are more reduced data flow, less latency, and higher dynamic range.
A Chaotic Switched-Capacitor Circuit for Characteristic CMOS Noise Distributions Generation
N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2017
resumen
A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position of the corner frequency. Behavioural models simulations were carried on in Cadence Virtuoso in order to prove the correct functionality of the proposed approach.
SPAD-Sensor Camera Prototype for 2D/3D Imaging
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2017
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This demo presents a camera prototype based on a SPAD (single-photon avalanche diode) image sensor for 2D/3D scene reconstruction. SPADs are intrinsically binary devices that fire at the detection of a single photon entering the capture volume. They can be employed in photon counting mode, which provides a pixel output that is proportional to the brightness of the corresponding object in the scene. They can be employed also in combination with a time-to-digital converter (TDC), in order to provide a timestamp from which the time-of-flight (ToF) of the light reflected by the objects can be inferred, and thus their distance to the objective. In the first case, illumination does not have a structure. In the second case, a pulsed laser with
picosecond jitter is required to ensure the appropriate accuracy in the estimation of the distances. The prototype camera presented here employs a 64×64 SPAD array with active quenching and recharge and in-pixel TDC, allowing high frame rate acquisition. Highly efficient circuit design techniques are employed to ensure image capturing under a high level of uncorrelated noise such as dark count and background illumination. It has a depth resolution of 1cm at 6-0.1nW/mm2 illumination power.
VCRO-based TDCs in submicron CIS technology
F.N. Bandi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2017
resumen
Time-to-Digital Converters (TDCs) based on Voltage Controlled Ring Oscillators (VCROs) provides
a good trade off between area occupation, time resolution and power consumption. These specifications
are determined by applications like nuclear medicine and high energy physics imaging, in which an accurate
timestamp of the detected photons is needed and small area footprint to maximize fill factor is desired. This
is specially true when the number of incident photons is low and oversampling is impossible. Other TDC architectures
like pulse stretching, Vernier delay lines, time amplification or multi-path gated ring oscillator are
able to provide finer time resolution at the price of higher area occupation and power consumption. If in sensor
intregation is desired, these area and power increments are prohibitive. VCROs provides a large number of
alternatives during the design phase, each one with their advantages and disadvantages. The first step is the
selection of the stage topology, that is, single-ended, differential and pseudo-differential. In this application,
pseudo-differential stages outperforms the other alternatives in terms of lower power consumption, lower jitter
and better noise rejection. The second step consist in the selection of a pseudo-differential stage using a common
metric. To this end, the two most used pseudo-differential stages were compared in terms of time resolution, by
using the small signal model and the GBW product. Analytical expression points out that pseudo-differential
stage with cross-coupled inverters have finer time resolution than pseudo-differential stage with cross-coupled
PMOS. Pre-layout simulations support the analytical expression and shows a clear difference between the time
resolution of each stage.
Pipeline AER Arbitration with Event Aging
J.A. Leñero-Bardallo, F. Pérez-Peña, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
resumen
We present a simple circuit to handle communication between cells of neuromorphic arrays. It allows cells to operate continuously without waiting for acknowledgement signals back from the AER (Address Event Representation) arbitration circuitry. The module also implements aging of cell petitions i.e., old petitions to access to the AER bus are automatically discarded to give priority to the more recent ones and alleviate the bus congestion. The new arbitration scheme has been implemented and tested. A particular application scenario with an image sensor with spiking pixels that sense light continuously is explained. Experimental data obtained with real visual scenes are provided.
Live Demonstration: Photon Counting and Direct ToF Camera Prototype Based on CMOS SPADs
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
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This demonstrator reveals the performance and features of a single photon avalanche diode (SPAD) camera prototype. It is aimed to 2D/3D vision by photon counting and direct time-of-flight (d-ToF), respectively. The imager is built on a standard CMOS technology without any opto flavor or high voltage option. The camera module consists of a 64×64 SPAD imager and a FPGA board for real time image reconstruction at 1kfps.
Photon Counting and Direct ToF Camera Prototype based on CMOS SPADs
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
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This paper presents a camera prototype for 2D/3D image capture in low illumination conditions based on single-photon avalanche-diode (SPAD) image sensor for direct time-of-flight (d-ToF). The imager is a 64×64 array with in-pixel TDC for high frame rate acquisition. Circuit design techniques are combined to ensure successful 3D image capturing under low sensitivity conditions and high level of uncorrelated noise such as dark count and background illumination. Among them an innovative time gated front-end for the SPAD detector, a reverse start-stop scheme and real-time image reconstruction at 1kfps are incorporated by the imager. To the best of our knowledge, this is the first ToF camera based on a SPAD sensor fabricated and proved for 3D image reconstruction in a standard CMOS process without any opto-flavor or high voltage option. It has a depth resolution of 1cm at an illumination power from less than 6nW/mm2 down to 0.1nW/mm2.
A 2.2 μW analog front-end for multichannel neural recording
J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2017
resumen
In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain amplifier (VGA). The proposed architecture employs highly power-noise efficient current reuse fully differential OTAs in the LNA stage and a fully differential folded cascode for the VGA stage. Simulation results in AMS 0.18μm validate the proposed architecture under process corners variations with an estimated power consumption of 2.2μm and 3.1 μVrms in-band noise.
In the quest of vision-sensors-on-chip: Pre-processing sensors for data reduction
A. Rodríguez-Vázquez, R. Carmona-Galán, J. Fernández-Berni, V. Brea, J.A. Leñero-Bardallo
Conference · IS&T International Symposium on Electronic Imaging 2017
resumen
This paper shows that the implementation of vision systems benefits from the usage of sensing front-end chips with embedded pre-processing capabilities -called CVIS. Such embedded pre-processors reduce the number of data to be delivered for ulterior processing. This strategy, which is also adopted by natural vision systems, relaxes system-level requirements regarding data storage and communications and enables highly compact and fast vision systems. The paper includes several proof-o-concept CVIS chips with embedded pre-processing and illustrate their potential advantages.
On the Design of Implantable Neural Recording Interfaces: A Case Study
A. Rodríguez-Vázquez
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2016
resumen
Abstract not avaliable
CMOS Image Sensors for Range Estimation and 3D Imaging
A. Rodriguez-Vazquez
Conference · International Exhibition on Image Technology and Equipment ITE 2016
resumen
Abstract not avaliable
Demo: Image Sensing Scheme Enabling Fully-Programmable Light Adaptation and Tone Mapping with a Single Exposure
J. Fernández-Berni, F.D.V.R. Oliveira, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2016
resumen
This demo showcases a High Dynamic Range (HDR) technique recently reported. We demonstrate that two intertwined photodiodes per pixel can perform tone mapping under unconstrained illumination conditions with a single exposure. The proposed technique has been implemented on a prototype smart image sensor achieving a dynamic range of 102dB. It opens the door to the realization of smart cameras and vision sensors capable of rendering HDR images free of artifacts without requiring any digital post-processing at all.
Non-Recursive Method for Motion Detection from a Compressive-Sampled Video Stream
M. Trevisi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2016
resumen
This presentation introduces a non-recursive algorithm for motion detection directly from the analysis of compressed samples. The objective of this research is to create an algorithm able to detect, in real-time, the presence of moving objects over a fixed background from a compressive-sampled greyscale video stream. Many difficulties arise using this type of algorithm because it violates the fundamental principles of compressive sensing reconstruction that lie beneath traditional recursive methods. Recursive reconstruction methods even if accurate need large amounts of time and resources because they aim to retrieve all of the information contained within a scene. Our method is based on two key considerations. The first is that the targeted information of a moving element compared to a fixed background is really small. The second is an appropriate choice of a sub-Gaussian compressive sampling strategy. Our aim is to reduce the focus of general reconstruction in order to retrieve only objects of interest. This has resulted in a lightweight fast detection algorithm. It can be used to process compressed samples derived from a video stream with a speed of 100fps in order to detect the presence of moving objects over a fixed background. We have compared the performance of our algorithm with a highly efficient reconstruction algorithm, NESTA, to understand which benefits and limitations we are facing while trying to handle compressive-sampled information without recurring to standard techniques. While trying to target specific information within the compressed samples thus not following a conventional reconstruction technique may deliver worse reconstruction errors it is also true that it can benefit from faster processing times (Fig. 1) opening the possibility to new applications of CS.
Image dynamic range extension by using stacked (unmatched) photodiodes in CMOS
R. Carmona-Galán, J. A. Leñero-Bardallo, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2016
resumen
Capturing images containing unevenly illuminated areas within the same frame is very useful in application fields like surveillance, assisted driving, intelligent transportation, or industrial applications with high intra-scene contrast. Without the appropriate dynamic range to allocate these diverse illumination values, obtaining a detailed view of the brightest zones can easily obscure other elements in the scene. In order to increase the image dynamic range within the same frame, different techniques have been developed: using a sensor with a companding scheme, providing the means to avoid saturation, or employing multiple image captures. The problem with multiple captures is that uncorrelation between the different integration times can generate inexistent edges and distort the interpretation of the scene. In order to realize multiple captures in parallel, we need to be simultaneously sensitive to different illumination ranges. CMOS technology offers a variety of devices to capture light in the visible and near infrared range. If a deep-n-well is available, these structures can be stacked so spatial alignment is obtained by construction (Fig. 1a). The conversion gain of the different photodiodes is defined by their capacitance per unit area (Fig. 1b); therefore each of them will render a different voltage for the same light intensity. This discrepancy in the response can be exploited to extract information from different illumination ranges simultaneously. In this way, light can be sensed in parallel with different conversion gains and the resulting output voltages can then be digitized and combined into a single digital word with a larger number of bits. This mechanism for dynamic range extension does not depend on the difference of exposure times, so artifacts related with unmatched dynamics in the sensor and the scene can be avoided.
Mixed-Signal Quadratic Operators for the Feature Extraction of Neural Signals
M. Delgado-Restituto, R. Fiorelli, M. Carrasco-Robles and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2016
resumen
This paper presents design principles for reusing charge-redistribution SAR ADCs as digital multipliers. This is illustrated with an 8-b fully-differential rail-to-rail SAR ADC/multiplier, designed in a 180nm HV CMOS technology. This reconfigurability property can be exploited for the extraction of product-related features in neural signals, such as energy content, or for the discrimination of spikes using the Teager operator.
A 76nw, 4ks/S 10-Bit SAR ADC with Offset Cancellation for Biomedical Applications
M. Delgado-Restituto, M. Carrasco Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2016
resumen
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.
A Low-Energy 10-bit SAR ADC with Embedded Offset Cancellation
M. Delgado-Restituto, M. Carrasco-Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
resumen
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.
Integer-based digital processor for the estimation of phase synchronization between neural signals
J.B. Romaine, M. Delgado-Restituto, J.A. Lenero-Bardallo and A. Rodriguez-Vazquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2016
resumen
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. The low area and power consumptions make the processor an extremely scalable device which would work well in closed loop neural prosthesis for the treatment of neural diseases.
A 4-Mode Reconfigurable Low Noise Amplifier for Implantable Neural Recording Channels
J.L. Valtierra, A. Rodriguez-Vazquez and M. Delgado-Restituto
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2016
resumen
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by cicuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.
Non-Recursive Method for Motion Detection from a Compressive-Sampled Video Stream
M. Trevisi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2016
resumen
This paper introduces a non-recursive algorithm for motion detection directly from the analysis of compressed samples. The objective of this research is to create an algorithm able to detect, in real-time, the presence of moving objects over a fixed background from a compressive-sampled greyscale video stream. Many difficulties arise using this type of algorithm because it violates the fundamental principles of compressive sensing reconstruction that lie beneath traditional recursive methods. Recursive reconstruction methods even if accurate need large amounts of time and resources because they aim to retrieve all of the information contained within a scene. Our method is based on two key considerations. The first is that the targeted information of a moving element compared to a fixed background is really small. The second is an appropriate choice of a sub-Gaussian compressive sampling strategy. Our aim is to reduce the focus of general reconstruction in order to retrieve only objects of interest. This algorithm can be used to process compressed samples derived from a video stream with a speed of 100fps. This makes possible to detect the presence of moving objects directly from compressed samples with limited resources.
Highly scalable real time epilepsy diagnosis architecture via phase correlation and functional brain maps
J.B. Romaine, L. Acasandrei, M. Delgado-Restituto, A. Rodríguez-Vázquez
Conference · World Congress on Biosensors BIOSENSORS 2016
resumen
The complexity of biomedical neural processing is evident, with vast amounts of data needing to be handled and processed in order to reveal possible biomarkers which may lead to the early diagnosis of certain neurological disorders. One disorder in particular is epilepsy which is the most common neurological disorder in the world today affecting an estimated 50 million people.
Our proposed architecture is a highly efficient, scalable and low powered solution for the diagnosis and verification of epilepsy via the identification of changes in synchronicity between inter-ictal neural recording signals and functional brain maps. This multipurpose diagnosis system is realized as a mixture of clever data handling and sixteen real time phase synchronization processors which have a total capability of calculating the phase correlation of an entire brain map set of 120 neural signal combinations, gathered from 16 inter-ictal recording electrode positions located around the brain. Such a design could eventually lead to prediction of epilepsy via the detection of complex biomarkers.
In order for real time calculations to be possible we use a combination of smart pipelining and control logic. The processors calculate the phase correlation over the brain map via the means of accumulative sample differences from minimum to minimum transition periods between neural signals on sample by sample basis. This performs extremely well when compared to other more intense diagnostic calculation methods such as extraction of instantaneous phase angles.
The proposed architecture favours an ASCI design that drastically reduces the number of phase correlation calculation elements and cluttered interconnects and in turn infers a potentially low powered system.
Demo: HDR image sensor with linear response and asynchronous detection of saturation
J.A. Leñero-Bardallo, R. Carmona-Galan and A. Rodriguez-Vazquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2016
resumen
Abstract not avaliable
Pixel-wise parameter adaptation for single-exposure extension of the image dynamic range
R. Carmona-Galán, J.A. Leñero-Bardallo, J. Fernández-Berni and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2016
resumen
pdf
High dynamic range imaging is central in application fields like surveillance, intelligent transportation and advanced driving assistance systems. In some scenarios, methods for dynamic range extension based on multiple captures have shown limitations in apprehending the dynamics of the scene. Artifacts appear that can put at risk the correct segmentation of objects in the image. We have developed several techniques for the on-chip implementation of single-exposure extension of the dynamic range. We work on the upper extreme of the range, i. e. administering the available full-well capacity. Parameters are adapted pixel-wise in order to accommodate a high intra-scene range of illuminations.
Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips
R. Carmona-Galán, J. Fernández Berni and A. Rodríguez-Vázquez
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2016
resumen
pdf
Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementation.
In-Pixel Voltage-Controlled Ring-Oscillator for Phase Interpolation in ToF Image Sensors
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
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The design and measurements of a CMOS pseudo-differential voltage-controlled ring-oscillator (VCRO) are presented. It is aimed to act as time interpolator for arrayable picosecond time-to-digital convertors (TDC). This design is incorporated into a 64×64 array of TDCs for time-of-flight (ToF) measurement. It has been fabricated in a 0.18µm standard CMOS technology. Small occupation area of 28×29μm2 and low average power consumption of 1.17mW at 850MHz are promising figures for this application field. Embedded phase alignment and instantaneous start-up time are required to minimize the offset of time interval measurements. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of 102dBc/Hz at 2MHz offset frequency from 850MHz.
Hardware-Aware Performance Evaluation for the Co-Design of Image Sensors and Vision Algorithms
C. Villegas-Pachón, R. Carmona-Galán, J. Fernández-Berni and A. Rodríguez-Vázquez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2016
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The top-down approach to system design allows obtaining separate specifications for each subsystem. In the case of vision systems, this means propagating system-level specifications down to particular specifications for e. g. the image sensor, the image processor, etc. This permits to adopt different design strategies for each one of them, as long as they meet their own specifications. This approach can lead to over-design, which is not always affordable. Conversely, if higher-level specifications are too tight, they can lead to impossible specifications at the lower levels. This is certainly the case for embedded vision systems in which high-performance needs to be paired with a very restricted power budget. In order to explore alternative architectures, we need tools that allow for simultaneous optimization of different blocks. However, the link between low-level non-idealities and high-level performance is missing. CAD tools for the design and verification of analog and mixed-signal integrated circuits are not well suited for the simulation of higher-level functionalities. Our approach is to extract relevant data from circuit-level simulation and to build an OpenCV model to be employed in the design of the algorithm. The utility of this approach is illustrated by the evaluation of the effect of column-wise and pixel-wise FPN at the sensor on the performance of Viola-Jones face detection.
Live Demonstration: Single-Exposure HDR Image Acquisition Based on Tunable Balance Between Local and Global Adaptation
J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
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This live demonstration showcases a high dynamic range technique that compresses wide ranges of illuminations into the available signal range with a single exposure. In order to accomplish such compression, concurrent sensing-processing takes place at the focal plane, weighing the influence of local and global illumination on each pixel response during the image capture. This process is driven by an on-line analysis of the image histogram that also enables the dynamic accommodation of changing illumination conditions. The proposed technique has been implemented on a prototype smart image sensor achieving a dynamic range of 102dB.
Focal-plane scale space generation with a 6T pixel architecture
F. Oliveira, J.G. Gomes, R. Carmona-Galán, J. Fernández-Berni and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2016
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Fill factor and focal-plane implementation of instrumental image processing steps, we propose a simple modification in a standard pixel architecture in order to allow for charge redistribution among neighboring pixels. As a result, averaging operations may be performed at the focal plane, and image smoothing based on Gaussian filtering may thus be implemented. By averaging neighboring pixel values, it is also possible to generate intermediate data structures that are required for the computation of Haar-like features. To show that the proposed hardware is suitable for computer vision applications, we present a systemlevel comparison in which the scale-invariant feature transform (SIFT) algorithm is executed twice: first, on data obtained with a classical Gaussian filtering approach, and then on data generated from the proposed approach. Preliminary schematic and extracted layout pixel simulations are also presented.
A high dynamic range linear vision sensor with event asynchronous and frame-based synchronous operation
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2016
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We present a novel High-Dynamic-Range (HDR) image sensor with linear output. Photogenerated charge is continuously integrated at every pixel without saturating. Each time the photodiode voltage reaches a programmable threshold, the pixel resets and starts over integrating charge again. With an eventbased approach, it is possible to count the number of times (if any) that a pixel has saturated during exposure. Pixel illumination is represented with a 20-bit word. The most significant 12b represent the number of times that a pixel has saturated during exposure. The least significant 8b are the result of an analog-todigital conversion in the end of exposure. Thus, pixels provide linear outputs proportional to light intensity. A dynamic range of 120dB is expected. The maximum dynamic range that can be measured is limited by the maximum event rate that the chip peripheral circuitry can handle and by the space dedicated on memory to store the event information. Pixel pitch is 25μm. A prototype sensor with 128 x 96 pixels has been implemented in the AMS 180nm CMOS-HV technology. In this article, the pixel operation will be explained. Preliminary experimental results and snapshots will be also provided.
High-Level Performance Evaluation of Object Detection Based on Massively Parallel Focal-Plane Acceleration Requiring
Minimum Pixel Area Overhead
E. Parra-Barrero, J. Fernández-Berni, F.D.V.R. Oliveira, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Conference on Computer Vision Theory and Applications VISAPP 2016
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Smart CMOS image sensors can leverage the inherent data-level parallelism and regular computational flow of early vision by incorporating elementary processors at pixel level. However, it comes at the cost of extra area having a strong impact on the sensor sensitivity, resolution and image quality. In this scenario, the fundamental challenge is to devise new strategies capable of boosting the performance of the targeted vision pipeline while minimally affecting the sensing function itself. Such strategies must also feature enough flexibility to accommodate particular application requirements. From these high-level specifications, we propose a focal-plane processing architecture tailored to speed up object detection via the Viola-Jones algorithm. This architecture is supported by only two extra transistors per pixel and simple peripheral digital circuitry that jointly make up a massively parallel reconfigurable processing lattice. A performance evaluation of the proposed scheme in terms of accuracy and acceleration for face detection is reported.
In the quest of vision-sensors-on-chip: Pre-processing sensors for data reduction
A. Rodríguez-Vázquez
Conference · ITE Yokohama Trade Fair, 2015
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Abstract not avaliable
Smart CMOS Imagers for 2D and 3D Vision
A. Rodríguez-Vázquez
Conference · PhD School of the Annual meeting of the Associazione Gruppo Italiano di Elettronica GE 2015
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Abstract not avaliable
Why and How Making Image Sensors Moore Intelligent?
A. Rodríguez-Vázquez
Conference · Annual meeting of the Associazione Gruppo Italiano di Elettronica GE 2015
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Abstract not avaliable
ADCs for Imaging Applications. Comparative Overview and Some Improved Architectures
A. Rodríguez-Vázquez
Conference · Image Sensors 2015
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Abstract not avaliable
Interfacing Brain and Machines: Challenges and Perspectives
A. Rodriguez-Vazquez
Conference · International Conference on Computer as a Tool EUROCON 2015
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Summary form only given. Interfacing brain and machines involve recording neural signals, extracting information from them and applying stimulations in closed loop. Applications are huge: from therapies for epilepsy and other kind of brain seizures to the control of prosthesis. Challenges are enormeous and truly multidisciplinary: including, design of ultra low-noise microelectronic circuits with minimum power budget, energy scavenging, bio-compatibility, compressive sensing, etc. This talk identifies critical challenges and overviews proposed solutions. Discussions are illustrated with actual circuits tested in animals in collaboration between the Institute of Microelectronics of Seville, the University of Seville and the Institute of Bioengineering of the School of Medicine of the Universidad Miguel Hernandez.
Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs
R. Fiorelli, O. Guerra, R. del Rio and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors. To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and effective capacitors' value is obtained with an electrical extraction tool using a flattened view of the MOM. Effects of capacitors layout placement in the SAR and their surroundings in the effective capacitance value are quantified. A quantitative study of a 10-bit un-even split-capacitor SAR is done for different combinations of m and l bits. Finally, a qualitative set of guidelines to choose the distribution of these bits is listed.
Architectures and circuits for neural recording interfaces
A. Rodríguez-Vázquez
Conference · Selected Topics on Advanced Research on Circuits and Systems STAR-CAS 2015
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Interfacing brain and machines involve recording neural signals, extracting information from them and applying stimulations in closed loop. Applications are huge: from therapies for epilepsy and other kind of brain seizures to the control of prosthesis. Challenges are enormeous and truly multi-disciplinary: including, design of ultra low-noise microelectronic circuits with minimum power budget, energy scavenging, bio-compatibility, compressive sensing, etc. This talk identifies critical challenges and overviews proposed solutions. Discussions are illustrated with actual circuits tested in animals in collaboration between the Institute of Microelectronics of Seville, the University of Seville and the Institute of Bioengineering of the School of Medicine of the Universidad Miguel Hernandez.
On the Design of a Sparsifying Dictionary for Compressive Image Feature Extraction
M. Trevisi, R. Carmona-Galán, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2015
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Although there are some works reported on feature extraction from compressed samples, none of them consider the implementation of the feature extractor as a part of the sensor itself. Our approach is to introduce a sparsifying dictionary, feasibly implementable at the focal plane, which describes the image in terms of features. This allows a standard reconstruction algorithm to directly recover the interesting image features, discarding the irrelevant information. In order to validate the approach, we have integrated a Harris-Stephens corner detector into the compressive sampling process. We have evaluated the accuracy of the reconstructed corners compared to applying the detector to a reconstructed image.
CMOS Image Sensor Architecture for Focal Plane Early Vision Processing
F.D.V.R. de Oliveira, J.G.R.C. Gomes, R. Carmona-Galán, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2015
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This paper presents a pixel architecture that aims at validating the idea that with a small change in the pixel it is possible to perform important image processing computations at the focal-plane without significantly affecting the fill factor. An overview of two algorithms that may benefit from this new pixel architecture is given, namely the SIFT for object recognition and the Viola-Jones for face detection. A brief discussion of the limitations of the computations performed inside the pixel matrix and the future work is also presented.
Hardware-oriented feature extraction based on compressive sensing
M. Trevisi, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2015
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Feature extraction is used to reduce the amount of resources required to describe a large set of data. A given feature can be represented by a matrix having the same size as the original image but having relevant values only in some specific points. We can consider this sets as being sparse. Under this premise many algorithms have been generated to extract features from compressive samples. None of them though is easily described in hardware. We try to bridge the gap between compressive sensing and hardware design by presenting a sparsifying dictionary that allows compressive sensing reconstruction algorithms to recover features. The idea is to use this work as a starting point to the design of a smart imager capable of compressive feature extraction. To prove this concept we have devised a simulation by using the Harris corner detection and applied a standard reconstruction method, the Nesta algorithm, to retrieve corners instead of a full image.
Compressive Feature Extraction
M. Trevisi, R. Carmona-Galán, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2015
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Compressive sensing (CS) provides an alternative to Nyquist-Shannon sampling when the signal to acquire is known to be sparse or compressible. A sparse signal has a small number of nonzero components compared to its total length. This property can either exist in the sampling domain of the signal or with respect to other basis. Representing a signal in a transform basis involves the choice of a dictionary, a set of elementary signals, used to decompose the signal. When performing analysis of complex data one of the major problems stems from the number of variables involved. Feature extraction is used to reduce the amount of resources required to describe a large set of data. A given feature is often represented by a set of parameters to be evaluated. This set has relevant values only in correspondence of said features. We can consider sets derived this way as being sparse. This sparked the idea to merge a feature extraction algorithm with the compressive sensing theory. To do so we try to adapt one of the most practical CS reconstruction algorithms, the Nesterov algorithm applied to CS (NESTA) to extract the features of one of the simplest corner detection algorithms, the Harris and Stephens algorithm. Our aim is to compare the performance of the combined Harris-NESTA algorithm over the application of a Harris algorithm on a NESTA reconstructed image and to do so we devised a test that takes into account four different parameters.
A high dynamic range image sensor with linear response based on asynchronous event detection
J.A. Leñero-Bardallo, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2015
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This paper investigates the potential of an image sensor that combines event-based asynchronous outputs with conventional integration of photocurrents. Pixels voltages can be read out following a traditional approach with a source follower and analog-to-digital converter. Furthermore, pixels have circuitry to implement Pulse Density Modulation (PDM) sending out pulses with a frequency that is proportional to the photocurrent. Both read-out approaches operate simultaneously. Their information is combined to render high dynamic range images. In this paper, we explain the new vision sensor concept and we develop a theoretical analysis of the expected performance in standard AMS 0.18 µm HV technology. Moreover, we provide a description of the vision sensor architecture and its main blocks.
Live demonstration: Gaussian pyramid extraction with a CMOS vision sensor
M. Suarez, V.M. Brea, J. Fernandez-Berni, R. Carmona-Galan, D. Cabello and A. Rodriguez-Vazquez
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2015
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This live demonstration is related to ISCAS track 'Imagers and Vision Processing'. It showcases the Gaussian pyramid with a CMOS vision sensor with a 176 × 120 pixel array in standard 0.18 μm CMOS technology. The sensing elements are 3T-APS with in-pixel ADC and CDS. The Gaussian pyramid is extracted concurrently with a double-Euler switched-capacitor network on the same substrate, giving RMSE errors below 1.2% of FSO. The chip provides a Gaussian pyramid of 3 octaves with 6 scales each with an energy cost of 26.5 nJ/px at 2.64 Mpx/s.
Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression
S. Vargas-Sierra, G. Liñan-Cembrano and A. Rodriguez-Vazquez
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2015
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This demonstration targets the acquisition of realtime video sequences involving High Dynamic Range (HDR) scenes. Adaptation to different illumination conditions while preserving contrast is achieved by using a sensor chip, which implements an adaptive content-aware tone mapping compression algorithm by using in-pixel circuitry. Its response gets adapted to changing illumination conditions by using at each frame a statistical estimation of the light distribution, which is derived from the HDR histogram calculated at the previous frame. This method allows adaptive HDR video, while capable to capture very large DR scenes including moving objects.
A 64-channel ultra-low power system-on-chip for local field and action potentials recording
A. Rodríguez-Pérez, M. Delgado-Restituto, A. Darie, C. Soto-Sánchez, E. Fernández-Jover and Á. Rodríguez-Vázquez
Conference · SPIE Micro Technologies, 2015
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This paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other,feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330μW.
Automatic DR and spatial sampling rate adaptation for secure and privacy-aware ROI tracking based on focal-plane image processing
R. Carmona-Galán, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · International Image Sensor Workshop IISW 2015
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Embedded camera systems for the consumer mobile and wearable application market need to operate in a tight power budget. They need to cope with a vast range of illumination conditions, and at the same time, they need to incorporate enough intelligence to implement security and privacy-protection directives. The incorporation of image signal processing at the focal-plane can help reducing the necessary resources to implement tasks like DR adaptation and privacy-aware ROI tracking. In this paper we present a vision sensor that is able to perform single-exposure HDR imaging and ROI obfuscation on-chip, with the help of a reduced set of focal-plane processing elements.
On the Calibration of a SPAD-Based 3D Imager with in-Pixel TDC Using a Time-Gated Technique
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
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The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. The overall full-width half-maximum (FWHM) of the detector ensemble SPAD plus TDC is 690ps. The sensor has been fabricated in a 0.18μm standard CMOS technology which features an average dark-count rate (DCR) of 42Khz at 1V excess voltage (Ve) and room temperature. The detector successfully uses its time-gating capability to mitigate this large amount of noise enabling the sensor for accurate time-of-flight (ToF) measurements. The effectiveness of the time-gating technique is experimentally demonstrated. According to measurements, a time window of 400ns is enough to ensure that the TDC is triggered by light rather than by spurious events.
Design Considerations for A Low-Noise CMOS Image Sensor
A. González-Márquez, A. Charlet, A. Villegas, F. Jiménez-Garrido, F. Medeiro, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2015
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This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.
A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2015
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The design and measurements of a CMOS 64×64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reversed start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.
Real-time single-exposure ROI-driven HDR adaptation based on focal-plane reconfiguration
J. Fernández-Berni, R. Carmona-Galán, R. del Río, R. Kleihorst, W. Philips and Á. Rodríguez-Vázquez
Conference · SPIE Real-Time Image and Video Processing 2015
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This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of interest concurrently, automatically and asynchronously with a single exposure period. The operation is supported by two intertwined photo-diodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal-plane into independent regions within which automatic concurrent adjustment of the integration time takes place. At pixel level, one of the photo-diodes senses the pixel value itself whereas the other, in collaboration with its counterparts in a particular ROI, senses the mean illumination of that ROI. Additional circuitry interconnecting both photo-diodes enables the asynchronous adjustment of the integration time for each ROI according to this sensed illumination. The sensor can be reconfigured on-the-fly according to the requirements of a vision algorithm.
CMOS Single-Photon Avalanche Sensors and Imagers
A. Rodríguez-Vázquez
Conference · ITE Yokohama Trade Fair, 2014
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Abstract not avaliable
Vision Beyond Imaging Hybrid Cellular Architectures for High-Sensitivity, High-Speed, High-Resolution Vision Systems with Reduced SWaP
A. Rodríguez-Vázquez
Conference · Symposium on Emerging Trends in Electronics, 2014
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Abstract not avaliable
A CMOS 0.18μm 64x64 Single Photon Image Sensor with in-Pixel 11b Time-to-Digital Converter
I. Vornicu, R. Carmona and Á. Rodríguez-Vázquez
Conference · International Semiconductor Conference CAS 2014
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Abstract not avaliable
5x5 SPAD Matrices for the Study of the Trade-offs between Fill Factor, Dark Count Rate and Crosstalk in the Design of CMOS Image Sensors
M. Moreno-García, R. del Río, Ó. Guerra, and Á. Rodríguez-Vázquez
Conference · Conference on Ph.D. Research in Microelectronics and Electronics PRIME 2014
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CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. There are tradeoffs that involve these two magnitudes and dark count rate (DCR) which are of great interest for the implementation of image sensors. A set of 5x5 matrices of SPADs with different sizes and shapes is designed to study the relationships between FF, crosstalk and DCR, and conceive an accurate behavioural model of SPAD arrays. The testchip is fully operative and preliminary experimental results are presented.
Live Demo: Real-time Focal-plane Face Obfuscation through Programmable Pixelation
J. Fernández-Berni, R. Carmona-Galán, R. del Río, J.A. Leñero-Bardallo, R. Kleihorsty, W. Philipsy and Á. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2014
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Privacy concerns are hindering the introduction of smart camera networks in application scenarios like retailing analytics, factories or elderly care. Indeed, there is usually no need of dealing with sensitive data when it comes to carrying out a meaningful visual analysis in these scenarios. Time spent by customers in front of a showcase, trajectories of workers around a manufacturing site or fall detection in a nursing home are three examples where video analytics can be performed without compromising privacy. But still the idea of networked cameras pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. New strategies must be developed in order to ensure privacy from the very point where sensitive data are generated: the sensors. Protection measures embedded on-chip at the front-end sensor of each network node significantly reduce the number of trusted system components as well as the impact of potential software flaws. In this demonstration, we present a full-custom QVGA vision sensor that can be reconfigured to implement programmable pixelation of image regions at the focal plane. According to the literature, pixelation provides the best performance in terms of balance between privacy protection and intelligibility of the surveyed scene.
A 330μW, 64-Channel Neural Recording Sensor with Embedded Spike Feature Extraction and Auto-calibration
A. Rodríguez-Pérez, M. Delgado-Restituto, A. Darie, C. Soto-Sánchez, E. Fernández-Jover and Á. Rodríguez-Vázquez
Conference · IEEE Asian Solid-State Circuits Conference A-SSCC 2014
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This paper reports a 64-channel neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results show that the power consumption of the complete system is 330μW.
In vivo measurements with a 64-channel extracellular neural recording integrated circuit
M. Delgado-Restituto, A. Rodríguez-Pérez, A.A. Darie, Á. Rodríguez-Vázquez, C. Soto-Sánchez and E. Fernández-Jover
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2014
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This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time data acquisition. This interface connects the ASIC to a conventional 2.0 USB port by means of a Field Programmable Gate Array (FPGA). Communications are bidirectional and employ custom protocols both for delivering commands to the ASIC and for recording neural information under different channel selection and operation modes. The link is controlled by a user-friendly programming interface written in C++ which includes a built-in routine to efficiently index and store the captured data. Mesurements demonstrate the suitability of the ASIC for capturing local field and action potentials with two different microelectrode array platforms.
Wide Range 8ps Incremental Resolution Time Interval Generator based on FPGA technology
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2014
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Accurate generation of picosecond-resolution wide-range time intervals has become a necessity for the characterization of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of timeto-digital converters. It can work as periodic pulse/ frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20ps RMS jitter over a time range of 600ps to 33μs. The incremental time resolution is 8ps and the repetition rate is up to 2MHz.The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field.
Demo: A prototype vision sensor for real-time focal-plane obfuscation through tunable pixelation
J. Fernández-Berni, R. Carmona-Galán, R. del Río, R. Kleihorst, W. Philips and A. Rodríguez-Vázquez
Conference · IEEE/ACM Int. Conference on Distributed Smart Cameras ICDSC 2014
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Privacy concerns are hindering the introduction of smart camera networks in prospective application scenarios like retail analytics, factory monitoring or elderly care. The idea of networked cameras pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. New strategies must be developed in order to ensure privacy from the very point where sensitive data are generated: the sensors. Protection measures embedded on-chip at the front-end sensor of each network node significantly reduce the number of trusted system components as well as the impact of potential software flaws. In this demonstration, we present a full-custom QVGA vision sensor that can be recongured to implement programmable pixelation of image regions at the focal plane. In particular, we show on-the-fly focal-plane face obfuscation supported by the Viola-Jones frontal face detector provided by OpenCV.
A 26.5 nJ/px 2.64Mpx/s CMOS vision sensor for gaussian pyramid extraction
M. Suárez-Cambre, V. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello and A. Rodríguez-Vázquez
Conference · European Solid-State Circuits Conference ESSCIRC 2014
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This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. The chip, manufactured in a 0.18 μm CMOS technology, consists of an arrangement of 88×60 processing elements (PEs) which captures images of 176×120 resolution and performs concurrent parallel processing right at pixel level. The Gaussian pyramid is generated by using a switched-capacitor network. Every PE includes four photodiodes, four MiM capacitors, one 8-bit single-slope ADC and one CDS circuit, occupying 44x44 μm2 . Suitability of the chip is assessed by using metrics pertaining to visual tracking.
Fire detection with a frame-less vision sensor working in the NIR band
J.A. Leñero-Bardallo, J. Fernández-Berni, R. Carmona-Galán, P. Häfliger and Á. Rodríguez-Vázquez
Conference · International Conference on Forest Fire Research ICFFR 2014
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This paper draws the attention of the community about the capabilities of an emerging generation of bio-inspired vision sensors to be used in fire detection systems. Their principle of operation will be described. Moreover experimental results showing the performance of an event-based vision sensor will be provided. The sensor was intended to monitor flames activity without using optic filters. In this article, we will also extend this preliminary work and explore how its outputs can be processed to detect fire in the environment.
Review of ADCs for imaging
J.A. Leñero-Bardallo, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2014
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The aim of this article is to guide image sensors designers to optimize the analog-to-digital conversion of pixel outputs. The most common ADCs topologies for image sensors are presented and discussed. The ADCs specific requirements for these sensors are analyzed and quantified. Finally, we present relevant recent contributions of specific ADCs for image sensors and we compare them using a novel FOM.
A QVGA Vision Sensor with Multi-functional Pixels for Focal-Plane Programmable Obfuscation
J. Fernández-Berni, R. Carmona Galán, R. del Río and Á. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2014
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Privacy awareness constitutes a critical aspect for smart camera networks. An ideal awless protection of sensitive information would boost their application scenarios. However, it is still far from being achieved. Numerous challenges arise at diferent levels, from hardware security to subjective perception. Generally speaking, it can be stated that the closer to the image sensing device the protection measures take place, the higher the privacy and security attainable. Likewise, the integration of heterogeneous camera components becomes simpler since most of them will not require to consider privacy issues. The ultimate objective would be to incorporate complete protection directly into a smart image sensor in such a way that no sensitive data would be delivered off-chip while still permitting the targeted video analytics. This paper presents a 320x240-px prototype vision sensor embedding processing capabilities useful for accomplishing this objective. It is based on recongurable focal-plane sensing-processing that can provide programmable obfuscation. Pixelation of tunable granularity can be applied to multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise high dynamic range, integral image computation and Gaussian filtering. Its power consumption ranges from 42.6mW for high dynamic range operation to 55.2mW for integral image computation at 30fps. It has been fabricated in a standard 0.18μm CMOS process.
Towards an ultra-low-power low-cost wireless visual sensor node for fine-grain detection of forest fires
J. Fernández-Berni, R. Carmona-Galán, J.A. Leñero-Bardallo, R. Kleihorst and Á. Rodríguez-Vázquez
Conference · International Conference on Forest Fire Research ICFFR 2014
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Advances in electronics, sensor technologies, embedded hardware and software are boosting the application scenarios of wireless sensor networks. Specifically, the incorporation of visual capabilities into the nodes means a milestone, and a challenge, in terms of the amount of information sensed and processed by these networks. The scarcity of resources -power, processing and memory- imposes strong restrictions on the vision hardware and algorithms suitable for implementation at the nodes. Both, hardware and algorithms must be adapted to the particular characteristics of the targeted application. This permits to achieve the required performance at lower energy and computational cost. We have followed this approach when addressing the detection of forest fires by means of wireless visual sensor networks. From the development of a smoke detection algorithm down to the design of a low-power smart imager, every step along the way has been influenced by the objective of reducing power consumption and computational resources as much as possible. Of course, reliability and robustness against false alarms have also been crucial requirements demanded by this specific application. All in all, we summarize in this paper our experience in this topic. In addition to a prototype vision system based on a full-custom smart imager, we also report results from a vision system based on ultra-low-power low-cost commercial imagers with a resolution of 30x30 pixels. Even for this small number of pixels, we have been able to detect smoke at around 100 meters away without false alarms. For such tiny images, smoke is simply a moving grey stain within a blurry scene, but it features a particular spatio-temporal dynamics. As described in the manuscript, the key point to succeed with so low resolution thus falls on the adequate encoding of that dynamics at algorithm level.
Gaussian pyramid extraction with a CMOS vision sensor
M. Suárez, V.M. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello and A. Rodríguez-Vázquez
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2014
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This paper addresses a CMOS vision sensor with 176x120 pixels in standard 0.18 μm CMOS technology that computes the Gaussian pyramid. The Gaussian pyramid is extracted with a double-Euler switched-capacitor network, giving RMSE errors below 1.2% of full-scale value. The chip provides a Gaussian pyramid of 3 octaves with 6 scales each with an energy cost of 26.5 nJ at 2.64 Mpx/s.
Comparative Analysis of Compressive Sensing Strategies for Smart Compressive Image Sensors
M. Trevisi, R. Carmona-Galán, J. Fernández-Berni and Á. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2014
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Compressive sensing (CS) first appeared eight years ago as a new kind of signal processing theory. Since then, only a few steps have been taken to turn this theory into feasible practice. We have identified two important gaps that stand behind the lag on practical compressive image sensors. The first one is that, technologically speaking, there is not yet any imager based on CS that is able to overrule, at least in resolution/decryption-speed ratio, the capabilities of current standard imagers. The second one is that none of the published reports on compressive image sensors mention how the compressive sensing strategy is passed from the sensor, which is delivering image samples, to the image reconstruction algorithm at the reception side. In order to capture compressed image samples, it is necessary that the imagers implement a compressive strategy, which has the form of a matrix that convolves the original signal. There are two sets of methods that are primarily implemented nowadays to build a compressive strategy, the first one is to pick each element from a random distribution, preferably Gaussian, and the second is to arrange in random order the rows of an incoherent orthobasis matrix, preferably Fourier matrix. The selection of the compressive sensing strategy has an incidence on the physical implementation, for instance it is easier to implement a binary mask on each pixel than to multiply its value by a real number. In order to analyze the effect of this selection in the reconstruction from the samples delivered by the compressive image sensor, we have simulated the process with a MATLAB test bench and compared the reconstruction times and the RMSE vs. the number of samples delivered of three different sensing strategies using a 64×64 image of Lena as test image and a Total Variation NESTA algorithm as reconstruction algorithm.
Parallel Processing Architectures and Power Efficiency in Smart Camera Chips
R. Carmona-Galán, J. Fernández-Berni, M. Trevisi and A. Rodríguez-Vázquez
Conference · Workshop on the Architecture of Smart Cameras WASC 2014
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Because of the massive amount of data, image and video processing represents a huge computational demand. Providing the necessary resources in embedded systems is not an easy task. Providing them on-chip needs a serious reconsideration of the processing architecture. In order to speed up processing, the number of processors/cores operating in parallel can be increased. This is an intuitive result, but there are two drawbacks. First, this speedup is limited by the degree to which the algorithm can be parallelized, what is known as Amdahl's law. Second, the more hardware operating at the same time the higher the power consumption. However, image processing and, in general, the processing visual information that keeps a retinotopic topology, affords an inherent parallelism that can be exploited to a great extent. Furthermore, there is an additional and less intuitive result of parallelization, which is that using a larger number of processors renders a more efficient implementation in terms of GOPS/W. Evidence of this can be found in massively parallel array processors. Their distributed architecture is adapted to the nature of the visual stimulus to the point that the amount of energy dedicated to data transmission and memory operations is largely reduced. The result is a power efficient implementation, perfectly suited for autonomous embedded vision systems working on a restricted power budget. This trend is observed in multi- and many-core processor chips, GPUs and different types of single-instruction multiple-data (SIMD) arrays containing from tens to hundreds of processing elements (PE). In the case of analog array processors, a similar relation is observed despite the fact that the disparity between design techniques, signal representation and the computation of the effective number of OPS advises against any sort of comparison.
Form Factor Improvement of Smart-Pixels for Vision Sensors through 3-D Vertically-Integrated Technologies
A. Rodríguez-Vázquez, R. Carmona-Galán, J. Fernández Berni, S. Vargas, J.A. Leñero, M. Suárez, V. Brea and B. Pérez-Verdú
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2014
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While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and control of data interchange. This additional circuitry enables data processing be realized concurrently with the acquisition of images which is instrumental to reduce the number of data needed to carry to information contained into images. This way, more efficient vision systems can be built at the cost of larger pixel pitch. Vertically-integrated 3D technologies enable to keep the advnatges of smart pixels while improving the form factor of smart pixels.
Smart imaging for power-efficient extraction of Viola-Jones local descriptors
J. Fernández-Berni, R. Carmona-Galán, R. del Río, J.A. Leñero-Bardallo, M. Suárez-Cambre and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2014
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In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors constitute inputs for trained classifiers which in turn enable diferent high-level vision tasks. While local descriptors certainly alleviate the computation load of subsequent processing stages by preventing them from handling raw images, they still have to deal with individual pixels. Feature vector extraction can thus become a major limitation for conventional embedded vision hardware. In this paper, we present a power-eficicient sensing-processing array conceived to provide the computation of integral images at diferent scales. These images are intermediate representations that speed up feature extraction. In particular, the mixed-signal array operation is tailored for extraction of Haar-like features. These features feed the cascade of classifiers at the core of the Viola-Jones framework. The processing lattice has been designed for the standard UMC 0.18μm 1P6M CMOS process. In addition to integral image computation, the array can be reprogrammed to deliver other early vision tasks: concurrent rectangular area sum, block-wise HDR imaging, Gaussian pyramids and image pre-warping for subsequent reduced kernel filtering.
A 176x120 Pixel CMOS Vision Chip for Gaussian Filtering with Massivelly Parallel CDS and A/D-Conversion
M. Suárez, V.M. Brea, D. Cabello, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2013
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This paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switched-capacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to that of a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5×5 mm2 with 0.18 μm CMOS technology, achieving an array of 176×120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44×44 μm2. The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.
An Ultra-Low-Power Voltage-Mode Asynchronous WTA-LTA Circuit
J. Fernández-Berni, R. Carmona-Galán and A. Rodríquez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2013
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This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.
A CMOS 8×8 SPAD Array for Time-of-Flight Measurement and Light-Spot Statistics
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2013
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The design and simulation of a CMOS 8 x 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of on-chip processing simplifies the interfacing of the array with the host system. The pixel pitch is 32μm, while the diameter of the quasi-circular active area of the SPADs is 12μm. The 113μm2 active area is surrounded by a T-well guard ring. The resulting breakdown voltage is 10V with a maximum excess voltage of 1.8V. The pixel incorporates a novel active quenching/reset circuit. The array has been designed to operate with a laser pulsed at 20Mhz. The overall time resolution is 115ps. Focal-plane statistics are obtained in digital format. The maximum throughput of the digital output buffers is 200Mbps.
A Battery-free 64-channel Neural Spike Wireless Sensor Array
A. Rodríguez-Pérez, J. Ruiz-Amaya, J. Masuch, J.A. Rodríguez-Rodríguez, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Bio-MEMS and Medical Microdevices Conference 2013
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This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.
Real-Time Remote Reporting of Motion Analysis with Wi-Flip
J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · Int. Workshop on Cellular Nanoscale Networks and their Applications CNNA 2012
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This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration of FLIP-Q, a prototype mixed-signal focal-plane array processor, and Imote2, a commercial WSN platform. The application consists in scanning the whole scene by sequentially analyzing small regions. Within each region, motion is detected by background subtraction. Subsequently, information related to that motion - intensity and location - is radio-propagated in order to remotely account for it. By aggregating this information along time, a motion map of the scene is built. This map permits to visualize the different activity patterns taking place. It also provides an elaborated representation of the scene for further remote analysis, preventing raw images from being transmitted. In particular, the scene inspected in this demo corresponds to vehicular traffic in a motorway. The remote representation progressively built enables the assessment of the traffic density.
CMOS SPADs Selection, Modeling and Characterization Towards Image Sensors Implementation
M. Moreno-García, O. Guerra, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Conference on Electronics, Circuits, and Systems ICECS 2012
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The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance.
A CMOS-3D Reconfigurable Architecture with In-pixel Processing for Feature Detectors
M. Suárez, V.M. Brea, F. Pardo, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International 3D System Integration Conference 3DIC 2012
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This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which in turn can be used for operations like object detection, image registration or tracking. The top tier of the architecture contains the image acquisition circuits in an array of 320 × 240 active photodiode sensors (APS) driving a smaller array of 160 × 120 analog processors for low-level image processing. The top tier comprises in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel Analog to Digital Converter (ADC). The reuse of circuits for different functions permits to have a small area for every pixel. The bottom tier of the architecture contains a frame buffer with a set of registers acting as a frame-buffer with a one-to-one correspondence with the analog processors in the top tier, the digital circuitry necessary for the extrema detection and the calculation of the first and second spatial derivatives in the image, as well as Harris and Hessian point detectors. For the time being, a behavioral model of the first tier including mismatch and feedthrough and charge injection errors is discussed. Also, a VHDL model for the bottom tier is addressed. The two-tier architecture is conceived for its implementation on the 130 nm CMOS-3D technology from Tezzaron. A companion chip will perform the higher-level operations as well as communications. In this technology an area of 300 μm2 per analog processor has been estimated. The architecture proposed for pyramid generation lets a frame rate of 180 frames/s for an ADC conversion time of 120 μs. The architecture has been proved with object detection for a given feature detector.
Control and Acquisition System for a High Dynamic Range CMOS Image Sensor
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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A control and acquisition system for the visualization of the images captured with a High Dynamic Range (HDR) CMOS Image Sensor is developed. The image sensor is inserted in a PCB system, which performs low level control, in communication with a PC software, which performs high level control and images visualization. In order to make it user-friendly, we have opted to use object-oriented method to implement the computer software. The system has an attractive interface, and it is easy to operate. It also includes additional functionalities, such as the increment of the frame rate, enhancement of human perception of details contained in the depicted scene and the possibility to display statistical data for illustrating the behavior of the chip.
High-speed global shutter CMOS machine vision sensor with high dynamic range image acquisition and embedded intelligence
F. Jiménez-Garrido, J. Fernández-Pérez, C. Utrera, J.M. Muñoz, M.D. Pardo, A. Giulietti, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Conference · Sensors, Cameras, and Systems for Industrial and Scientific Applications XIII IMAGING 2012
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High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, etc. Many of these applications call also for large spatial resolution, high sensitivity and the ability to detect images with large intra-frame dynamic range. This paper reports a CIS intelligent digital image sensor with 5.2Mpixels which delivers 12-bit fully-corrected images at 250Fps. The new sensor embeds on-chip digital processing circuitry for a large variety of functions including: windowing; pixel binning; sub-sampling; combined windowing-binning-subsampling modes; fixed-pattern noise correction; fine gain and offset control; color processing, etc. These and other CIS functions are programmable through a simple four-wire serial port interface.
Design of a smart camera SoC in a 3D-IC technology
R. Carmona-Galán, J. Fernández-Berni, S. Vargas-Sierra, G. Liñán-Cembrano, A. Rodríguez-Vázquez, V. Brea-Sánchez, M. Suárez-Cambre and D. Cabello-Ferrer
Conference · Workshop on Architecture of Smart Camera, 2012
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Conventional digital signal processing architectures introduce data bottlenecks and are inefficient when dealing with multidimensional sensory signals; Architectures adapted to the nature of the stimulus are more efficient in terms of power consumption per operation but¿;Concurrent sensing, processing and memory in planar technologies introduces serious limitations to image resolution and image size via the penalties in fill factor and pixel pitch; 3D integrated circuit technologies with a dense TSV distribution permits eliminating data bottlenecks without degrading image resolution and size.
A 148dB focal-plane tone-mapping QCIF imager
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
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This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by an in-pixel tone-mapping scheme [1]. The tone mapping curve (TMC) is calculated from the histogram of an auxiliary previous image, which serves as a probability indicator of the distribution of illuminations within the current frame. The chip maps 148dB scenes onto 7-bit/pixel coding, containing illuminations from 2.2mlux (SNR10) to 55.33klux -with extreme values captured at 8s and 2.34μs, respectively. Pixels use an Nwell-Psubstrate photodiode and autozeroing for establishing the reset voltage. Measured sensitivity is 5.79 V over lux·s. Dark current effects in the final image are attenuated by an automatic programming of the DAC levels. The chip has been fabricated in the 0.35μm OPTO technology from AMS.
Power-efficient focal-plane image representation for extraction of enriched Viola-Jones features
J. Fernández-Berni, L. Acasandrei, R. Carmona-Galán, A. Barriga-Barrios and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
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This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an image representation which dramatically reduces the computational load of the Viola-Jones object detection framework. Additionally, such representation provides richer information than the simple sum of pixels within rectangular regions originally defined in this framework. As a result, more elaborated features could be devised to speed up the execution of the subsequent attentional cascade, boosting thus the performance of the whole algorithm. The proposed circuitry has been successfully implemented in a CMOS prototype smart imager. Experimental results are given, demonstrating the suitability of the approach presented to efficiently deliver enriched Viola-Jones features.
In-pixel generation of gaussian pyramid images by block reusing in 3D-CMOS
M. Suárez, V.M. Brea, D. Cabello, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
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This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generation. Gaussian pyramids are used in modern scale-and rotation-invariant feature detectors or in visual attention. Our switched-capacitor architecture is conceived within the framework of a CMOS-3D-based vision system. As such, it is also used during the acquisition phase to perform analog storage and Correlated Double Sampling (CDS). The paper addresses mismatch, and switching errors like feedthrough and charge injection. The paper also gives an estimate of the area occupied by each pixel on the 130nm CMOS-3D technology by Tezzaron. The validity of our proposal is assessed through object detection in a scale-and rotation-invariant feature detector.
A 176x144 148dB adaptive tone-mapping imager
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference · Sensors, Cameras, and Systems for Industrial and Scientific Applications XIII IMAGING 2012
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This paper presents a 176x144 (QCIF) HDR image sensor where visual information is simultaneously captured and adaptively compressed by means of an in-pixel tone mapping scheme.(1) The tone mapping curve (TMC) is calculated from the histogram of a Time Stamp image captured in the previous frame, which serves as a probability indicator of the distribution of illuminations within the present frame. The chip produces 7-bit/pixel images that can map illuminations from 311 mu lux to 55.3 klux in a single frame in a way that each pixel decides when to stop observing photocurrent integration-with extreme values captured at 8s and 2.34 mu s respectively. Pixels size is 33x33 mu m(2), which includes a 3x3 mu m(2) Nwell-Psubstrate photodiode and an autozeroing technique for establishing the reset voltage, which cancels most of the offset contributions created by the analog processing circuitry. Dark signal (10.8mV/s) effects in the final image are attenuated by an automatic programming of the DAC top voltage. Measured characteristics are Sensitivity 5.79V/lux-s s, FWC 12.2ke(-),Conversion Factor 129(e(-)/DN), and Read Noise 25e(-). The chip has been designed in the 0.35 mu m OPTO technology from Austriamicrosystems (AMS). Due to the focal plane operation, this architecture is especially well suited to be implemented in a 3D (vertical stacking) technology using per-pixel TSVs.
Switched-capacitor networks for scale-space generation
F. Pozas-Flores, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, scale-space filtering is widely used in feature extractors as the Scale-Invariant Feature Transform (SIFT) algorithm. RC networks are posed as valid scale-space generators in focal-plane processing. Switched-capacitor networks are another alternative, as different topologies and switching rate offer a great flexibility. This work examines the parallel and the bilinear implementations as two different switched-capacitor network topologies for scale-space filtering. The paper assesses the validity of both topologies as scale-space generators in focal-plane processing through object detection with the SIFT algorithm.
A QCIF 145dB Imager For Focal Plane Processor Chips Using a Tone Mapping Technique in Standard 0.35μm CMOS Technology
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference · International Image Sensor Workshop IISW 2011
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This paper presents a QCIF HDR imager where visual informatioin is simultaneously captured and adptively compressed by means of an in-pixel tone mapping scheme. The tone mapping curve (TCM) is calculated from a non-linear histogram of the previous image, wich serves as a probability indicator of the distribution of illuminations within the present frame. The chip produces 7-bit/pixel images that can map illuminations from 311x10(-6)lux to 5875 lux in a single frame in a way that each pixel decides when to stop observing photocurrent integration -with exttreme values captured at 8s and 20μs respectively. Pixels use a 3x3μm2 Nwell-Psubstrate photodiode and an autozeroing technique for establishing the reset voltage, which cancels most of the offset contributions created by the analog processing circuitry. Measured sensitivity is 5.79 v/lux.s. Dark current effects in the final image are attenuated by an automatic programming of the DAC top voltage. The chip has been designed in the 0.35 μm OPTO technology from AMS.
A self-calibration circuit for a neural spike recording channel
A. Rodríguez-Pérez, J. Ruiz-Amaya, M. Delgado-Restituto, M. Sawan and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2011
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This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. It also performs the adjustment of the Programmable Gain Amplifier (PGA) gain to maximize the input voltage range of the analog-to-digital conversion. The circuit, which consists on a frequency-controlled signal generator and a digital processor, operates in foreground, is completely autonomous and integrable in an estimated area of 0.026mm 2, with a power consumption around 450nW. The calibration procedure takes less than 250ms to select the configuration whose performance is closest to the required one. © 2011 IEEE.
Image filtering by reduced kernels exploiting kernel structure and focal-plane averaging
J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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Incorporating multi-resolution capabilities into imagers renders additional power saving mechanisms in the subsequent image processing. In this paper, we show how, by exploiting a certain mask structure, 3 × 3 kernels can be reduced to 2 × 2 kernels if charge redistribution is provided at the focal plane of the imaging device. More precisely, by averaging and shifting a half-resolution pixel grid, we will have a pre-processed image, subsampled by a factor of 2 on each dimension, that can be filtered with a mask of a reduced size. Very useful image filtering kernels, like a 3 × 3 Gaussian kernel for image smoothing, or the well-known Sobel operators, fall into this category of reducible kernels. Operating onto the pre-processed image with one of these reduced kernels represents a smaller number of operations per pixel than realizing all the multiply-accumulate operations needed to apply a 3 × 3 kernel. Memory accesses are reduced in the same fraction. Concerning the difficulties of providing this pre-processed image representation, we propose a methodology for obtaining it at a very low power cost. It requires the implementation of user definable image subdivision and subsampling at the focal plane. Experimental results are given, obtained from measurements on a CMOS imager prototype chip incorporating these multi-resolution capabilities. © 2011 IEEE.
Demo: Real-time remote reporting of active regions with Wi-FLIP
J. Fernández-Berni, R. Carmona-Galán, G. Liñán-Cembrano, A. Zarándy and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2011
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This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration of FLIP-Q, a focal-plane low-power image processor, and Imote2, a commercial WSN platform. The application, though simple, shows the potentiality of the reduced scene representations achievable at FLIP-Q to speed up the processing. It consists of detecting the active regions within the scene being surveyed, that is, those regions undergoing thresholded variations with respect to the background. If an activity pattern is prescribed, FLIP-Q enables the reconfigurability of the image plane accordingly, making its detection and tracking easier. For each frame, the number of active regions is calculated and wirelessly reported in real time. A base station picks up the radio signal and sends the information to a PC via USB, also in real time. Frame rates up to around 10fps have been achieved, although it greatly depends on the light conditions and the image plane division grid. © 2011 IEEE.
Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor
J. Fernández-Berni, R. Carmona-Galán, G. Liñán-Cembrano, A. Zarándy and A. Rodríguez-Vázquez
Conference · International Conference on Distributed Smart Cameras ICDSC 2011
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This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, and Imotel, a commercial WSN platform. In Wi-FLIP, image processing is not only constrained to the digital domain like in conventional architectures. Instead, its image sensor - the FLIP-Q prototype - incorporates pixel-level processing elements (PEs) implemented by analog circuitry. These PEs are interconnected, rendering a massively parallel SIMD-based focal-plane array. Low-level image processing tasks fit very well into this processing scheme. They feature a heavy computational load composed of pixel-wise repetitive operations which can be realized in parallel with moderate accuracy. In such circumstances, analog circuitry, not very precise but faster and more area- and power-efficient than its digital counterpart, has been extensively reported to achieve better performance. The Wi-FLIP's image sensor does not therefore output raw but pre-processed images that make the subsequent digital processing much lighter. The energy cost of such pre-processing is really low - 5.6mW for the worst-case scenario. As a result, for the configuration where the Imote2's processor works at minimum clock frequency, the maximum power consumed by our prototype represents only the 5.2% of the whole system power consumption. This percentage gets even lower as the clock frequency increases. We report experimental results for different algorithms, image resolutions and clock frequencies. The main drawback of this first version of Wi-FLIP is the low frame rate reachable due to the non-standard GPIO-based FLIPQ-to-Imote2 interface. © 2011 IEEE.
A power efficient neural spike recording channel with data bandwidth reduction
A. Rodríguez-Pérez, J. Ruiz-Amaya, J.A. Rodríguez-Rodríguez, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2011
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This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13 mu m and occupies 400 mu mx400 mu m. The overall power consumption of the channel during signal tracking is 2.8 mu W and increases to 3.0 mu W average when the feature extraction operation mode is programmed.
An auto-calibrated neural spike recording channel with feature extraction capabilities
A. Rodríguez-Pérez, J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · SPIE Microtechnologies for the New Millennium 2011
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This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a self-calibration operation mode and can be used both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a PWL approximation of the spikes in order to reduce data bandwidth on the RF-link). The neural threshold voltage is adaptively calculated during the spike detection period using basic digital operations. The neural input signal is amplified and filtered using a LNA, reconfigurable Band-Pass Filter, followed by a fully reconfigurable 8-bit ADC. The key element is the ADC architecture. It is a binary search data converter with a SC-implementation. Due to its architecture, it can be programmed to work either as a PGA, S&H or ADC. In order to allow power saving, inactive blocks are powered off depending on the selected operation mode, ADC sampling frequency is reconfigured and bias current is dynamically adapted during the conversion. Due to the ADC low input capacitance, the power consumption of the input LNA can be decreased and the overall power consumption of the channel is low. The prototype was implemented using a CMOS 0.13um standard process, and it occupies 400um x 400um. Simulations from extracted layout show very promising results. The power consumption of the complete channel for the signal tracking operations is 2.8uW, and is increased to 3.0uW when the feature extraction operation is performed, one of the lowest reported.
High-dynamic range tone-mapping algorithm for focal plane processors
S. Vargas-Sierra, G. Liñan-Cembrano, E. Roca and A. Rodríguez-Vázquez
Conference · SPIE Microtechnologies for the New Millennium 2011
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This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors (FPP) due to its very limited computing requirements since only local memories, little digital control and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure time to create a 4-bit non-linear image whose histogram determines the shape of the tone-mapping curve which is applied to create the final image. Simulations results over a highly bimodal 120dB image are presented showing that both the highly and poorly illuminated parts of the image keep a sufficient level of details.
Multi-resolution low-power gaussian filtering by reconfigurable focal-plane binning
J. Fernández-Berni, R. Carmona-Galán, F. Pozas-Flores, A. Zarándy and A. Rodríguez-Vázquez
Conference · SPIE Microtechnologies for the New Millennium 2011
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Gaussian filtering is a basic tool for image processing. Noise reduction, scale-space generation or edge detection are examples of tasks where different Gaussian filters can be successfully utilized. However, their implementation in a conventional digital processor by applying a convolution kernel throughout the image is quite inefficient. Not only the value of every single pixel is taken into consideration sucessively, but also contributions from their neighbors need to be taken into account. Processing of the frame is serialized and memory access is intensive and recurrent. The result is a low operation speed or, alternatively, a high power consumption. This inefficiency is specially remarkable for filters with large variance, as the kernel size increases significantly. In this paper, a different approach to achieve Gaussian filtering is proposed. It is oriented to applications with very low power budgets. The key point is a reconfigurable focal-plane binning. Pixels are grouped according to the targeted resolution by means of a division grid. Then, two consecutive shifts of this grid in opposite directions carry out the spread of information to the neighborhood of each pixel in parallel. The outcome is equivalent to the application of a 3x3 binomial filter kernel, which in turns is a good approximation of a Gaussian filter, on the original image. The variance of the closest Gaussian filter is around 0.5. By repeating the operation, Gaussian filters with larger variances can be achieved. A rough estimation of the necessary energy for each repetition until reaching the desired filter is below 20nJ for a QCIF-size array. Finally, experimental results of a QCIF proof-of-concept focal-plane array manufactured in 0.35 mu m CMOS technology are presented. A maximum RMSE of only 1.2% is obtained by the on-chip Gaussian filtering with respect to the corresponding equivalent ideal filter implemented off-chip.
Design of a smart SiPM based on focal-plane processing elements for improved spatial resolution in PET
F. Pozas-Flores, R. Carmona-Galán, J. Fernández-Berni and A. Rodríguez-Vázquez
Conference · SPIE Microtechnologies for the New Millennium 2011
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Single-photon avalanche diodes are compatible with standard CMOS. It means that photo-multipliers for scintillation detectors in nuclear medicine (i. e. PET, SPECT) can be built in inexpensive technologies. These silicon photo-multipliers consist in arrays of, usually passively-quenched, SPADs whose output current is sensed by some analog readout circuitry. In addition to the implementation of photosensors that are sensitive to single-photon events, analog, digital and mixed-signal processing circuitry can be included in the same CMOS chip. For instance, the SPAD can be employed as an event detector, and with the help of some in-pixel circuitry, a digitized photo-multiplier can be built in which every single-photon detection event is summed up by a counter. Moreover, this concurrent processing circuitry can be employed to realize low level image processing tasks. They can be efficiently implemented by this architecture given their intrinsic parallelism. Our proposal is to operate onto the light-induced signal at the focal plane in order to obtain a more elaborated record of the detection. For instance, by providing some characterization of the light spot. Information about the depth-of-interaction, in scintillation detectors, can be derived from the position and shape of the scintillation light distribution. This will ultimately have an impact on the spatial resolution that can be achieved. We are presenting the design in CMOS of an array of detector cells. Each cell contains a SPAD, an MOS-based passive quenching circuit and drivers for the column and row detection lines.
Focal-plane generation of multi-resolution and multi-scale image representation for low-power vision applications
J. Fernández-Berni, R. Carmona-Galán, L. Carranza-González, A. Zarandy and A. Rodríguez-Vázquez
Conference · SPIE Infrared Technology and Applications XXXVII, 2011
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Early vision stages represent a considerably heavy computational load. A huge amount of data needs to be processed under strict timing and power requirements. Conventional architectures usually fail to adhere to the specifications in many application fields, especially when autonomous vision-enabled devices are to be implemented, like in lightweight UAVs, robotics or wireless sensor networks. A bioinspired architectural approach can be employed consisting of a hierarchical division of the processing chain, conveying the highest computational demand to the focal plane. There, distributed processing elements, concurrent with the photosensitive devices, influence the image capture and generate a pre-processed representation of the scene where only the information of interest for subsequent stages remains. These focal-plane operators are implemented by analog building blocks, which may individually be a little imprecise, but as a whole render the appropriate image processing very efficiently. As a proof of concept, we have developed a 176x144-pixel smart CMOS imager that delivers lighter but enriched representations of the scene. Each pixel of the array contains a photosensor and some switches and weighted paths allowing reconfigurable resolution and spatial filtering. An energy-based image representation is also supported. These functionalities greatly simplify the operation of the subsequent digital processor implementing the high level logic of the vision algorithm. The resulting figures, 5.6mW@30fps, permit the integration of the smart image sensor with a wireless interface module (Imote2 from Memsic Corp.) for the development of vision-enabled
On-site forest fire smoke detection by low-power autonomous vision sensor
J. Fernández-Berni, R. Carmona-Galán, L. Carranza-González, A. Cano-Rojas, J. F. Martínez-Carmona, A. Rodríguez-Vázquez and S. Morillas-Castillo
Conference · International Conference on Forest Fire Research ICFFR 2010
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Early detection plays a crucial role to prevent forest fires from spreading. Wireless vision sensor networks deployed throughout high-risk areas can perform fine-grained surveillance and thereby very early detection and precise location of forest fires. One of the fundamental requirements that need to be met at the network nodes is reliable low-power on-site image processing. It greatly simplifies the communication infrastructure of the network as only alarm signals instead of complete images are transmitted, anticipating thus a very competitive cost. As a first approximation to fulfill such a requirement, this paper reports the results achieved from field tests carried out in collaboration with the Andalusian Fire-Fighting Service (INFOCA). Two controlled burns of forest debris were realized (www.youtube.com/user/vmoteProject). Smoke was successfully detected on-site by the EyeRISTM v1.2, a general-purpose autonomous vision system, built by AnaFocus Ltd., in which a vision algorithm was programmed. No false alarm was triggered despite the significant motion other than smoke present in the scene. Finally, as a further step, we describe the preliminary laboratory results obtained from a prototype vision chip which implements, at very low energy cost, some image processing primitives oriented to environmental monitoring.
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3D technology
M. Suárez, V.M. Brea, C. Domínguez-Matas, R. Carmona, G. Liñán and A. Rodríguez-Vázquez
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2010
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This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS-3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW.
In-pixel ADC for a vision architecture on CMOS-3D technology
M. Suarez, V.M. Brea, C. Dominguez Matas, R. Carmona, G. Liñán and A. Rodríguez-Vázquez
Conference · IEEE 3D System Integration Conference 3DIC 2010
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This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a resolution of 320 × 240 pixels bump-bonded to a three-tier chip on the 150 nm FDSOI CMOS-3D technology from MIT-Lincoln Laboratories. The top tier is a mixed-signal layer with 160 × 120 processing elements. The ADC is distributed between the top two tiers. The top tier contains both global and local circuitry. The ramp generation is implemented with global circuitry through an 8-bit unary current-steering DAC. The end of conversion at every pixel or processing element is triggered by a local comparator. The digital words are stored in a frame-buffer in an intermediate tier. The area of the local circuitry in the ADC is consumed by the comparator, capable of reaching less than 3 mV of resolution in less than 150 ns with less than 220 μm2, and by the memory cells, each one storing 6 8-bit words along with two additional bits in less than 50 μm × 50 μm. Every ADC conversion is performed in less than 120 μs.
Circuital and Architectural Challenges for the Design of PET Medical Imaging Systems using CMOS
A. Rodríguez-Vázquez, R. Carmona-Galán, G. Liñán, R. del Río and B. Pérez-Verdú
Conference · International Workshop on Biomedical Applications of Micro-PET, 2010
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Abstract not available
A FPP-Oriented Tone Mapping Technique for High Dynamic Range Imagers Using Temporal and Final Exposure Measurements
S. Vargas-Sierra, G. Liñán-Cembrano, E. Roca-Moreno and A. Rodríguez-Vázquez
Conference · European Solid State Circuits Conference ESSCIRC 2010
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This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors due to its very limited computing requirements since only local memories and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure time to create a 4-bit artificial image whose histogram determines the shape of the tone-mapping curve which is applied to create the final image. Simulations results over a highiy bimodal120dB image are presented showing that both the highiy and poorly iiiuminated parts of the image keep a sufficient level of details.
Transformer based front-end for a low power 2.4 GHz transceiver
J. Masuch, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Asia-Pacific Conference on Circuits and Systems APCCAS 2010
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A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ohm antenna impedance to almost 1 kOhm and so facilitates a low power transmitter and receiver. The simulated post-layout output power of the differential class-E power amplifier is 2.0 dBm with a drain efficiency of 28.4%. The direct-conversion receiver achieves a very low power consumption of 420 uW and a noise figure of 15.0 dB. © 2010 IEEE.
A prototype node for wireless vision sensor network applications development
M. Bakkali, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Symposium on I/V Communications and Mobile Networks ISIVC 2010
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This paper presents a prototype vision-enabled sensor node based on a commercial vision system of reduced size and power consumption. The wireless infrastructure for the deployment of a distributed smart camera network based on these nodes is provided by commercial motes. The smart camera, based on a low-power bio-inspired processing scheme, enables in-node image processing and vision tools. This permits to elaborate a lighter representation of the scene, keeping the relevant information in terms of detected elements, features and events, alleviating the data transmission through the network. Therefore by passing only the relevant information to the neighboring sensor nodes, distributed and collaborative vision is possible with the limited data rates available in commercial wireless sensor networks. Communication between the different components of the system is supported by the available UARTs and GPIOs. Several examples of in-node image processing and feature detection has been tested in the prototype, and information at different abstraction levels has been broadcasted to the network. © 2010 IEEE.
Baseband-processor for a passive UHF RFID transponder
J.A. Rodríguez-Rodríguez, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · International Conference on Green Circuits and Systems ICGCS 2010
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This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been implemented in a 0.35um CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations confirm the fully functionality of the prototype and predict a worst-case power consumption of only 2.9uA at 1.2V supply. © 2010 IEEE.
A 3-D chip architecture for optical sensing and concurrent processing
A. Rodríguez-Vázquez, R. Carmona, C. Domínguez-Matas, M. Suárez-Cambre, V. Brea, F. Pozas, G. Liñán, P. Foldessy, A. Zarandy and C. Rekeczky
Conference · SPIE EUROPHOTONICS 2010
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This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5um x 5um pitch. © 2010 Copyright SPIE - The International Society for Optical Engineering.
Digital processor array implementation aspects of a 3D multi-layer vision architecture
P. Földesy, R. Carmona-Galán, Á. Zarándy, C. Rekeczky, A. Rodríguez-Vázquez and T. Roska
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2010
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Technological aspects of the 3D integration of a multi-layer combined mixed-signal and digital sensor-processor array chip is described. The 3D integration raises the question of signal routing, power distribution, and heat dissipation, which aspects are considered systematically in the digital processor array layer as part of the multi layer structure. We have developed a linear programming based evaluation system to identify the proper architecture and its parameters. © 2010 IEEE.
Simplified state update calculation for fast and accurate digital emulation of CNN dynamics
F. Pozas-Flores, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2010
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Compared to other one-step integration methods, the 4th-order Runge-Kutta is much more accurate while still consisting in a rather reduced algorithmic structure. However, in terms of the computing power, it is more expensive than others. While the Forward Euler's method updates the state variable with a single evaluation of the derivative, 4th-order Runge-Kutta's method requires four. This is the reason why, when simulation speed is a central matter, e. g. in the digital emulation of CNN dynamics, the speed-accuracy trade-off is resolved in favour of the simpler, though less accurate, methods. A workaround for the computationally intensive calculation of the state variable update can be found for certain CNN models. If a FSR CNN model is employed, where the state variable is not allowed to go beyond the limits of the linear region of the cell output characteristic, the output can be identified with the state. In these conditions, and having linear templates, the update of the state variable can be computed, for a 4th-order Runge-Kutta's method, with a single function evaluation. It means that a digital emulation of the CNN dynamics following this method is as light-weighted as a Forward Euler's integrator, but much more accurate. © 2010 IEEE.
A CMOS vision system on-chip with multicore sensory processing architecture for image analysis above 1,000F/s
A. Rodríguez-Vázquez, R. Domínguez-Castro, F. Jiménez-Garrido and S. Morillas
Conference · SPIE Sensors, Cameras, and Systems for Industrial/Scientific Applications XI, 2010
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This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand's frame-per-second rate. The chip employs a distributed processing architecture with a pre-processing stage consisting of an array of programmable sensory-processing cells, and a post-processing stage consisting of a digital microprocessor. The pre-processing stage operates as a retina-like sensor front-end. It performs parallel processing of the images captured by the sensors which are embedded together with the processors. This early processing serves to extract image features relevant to the intended tasks. The front-end incorporates also smart read-out structures which are conceived to transmit only these relevant features, thus precluding full gray-scale frames to be coded and transmitted. The chip is capable to close action-reaction loops based on the analysis of visual flow at rates above 1,000F/s with power budget below 1W peak. Also, the incorporation of processors close to the sensors enables signal-dependent, local adaptation of the sensor gains and hence high-dynamic range signal acquisition.
3D multi-layer vision architecture for surveillance and reconnaissance applications
P. Földesy, R. Carmona-Galan, A. Zarándy, C. Rekeczky, A. Rodríguez-Vázquez and T. Roska
Conference · European Conference on Circuit Theory and Design ECCTD 2009
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The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320x240 sensor array layer, closely coupled with a 160x120 mixed-signal processor array layer, a digital frame buffer layer, and an 8x8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS. ©2009 IEEE.
A low-power reconfigurable ADC for biomedical sensor interfaces
A. Rodríguez-Pérez, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · Biomedical Circuits and Systems Conference BIOCAS 2009
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This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC can be tuned to handle a large variety of biopotential signals, with digitally selectable resolution and input signal amplitude. It achieves 10.4-bit of effective resolution sampling at 56kS/s, with a power consumption below 3 mu W from a 1V voltage supply.
A focal plane processor for continuous-time 1-D optical correlation applications
G. Liñán-Cembrano, L. Carranza, B. Alexandre, E. Roca and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2009
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This paper describes a 1-D Focal Plane Processor incorporating 200 pixels for Continuous-Time Optical Correlation Applications. Each pixel incorporates a 2mmx10.9mm photodiode whose current is scaled, at the pixel level, by 5 independent 3-bit programmable-gain current amplifiers. Correlation patterns, defined as 5 sets of 200 3-bits numbers, are communicated to the chip via . a standard (IC)-C-2 interface. Correlation outputs are provided in current form through independent 8-bit-programmable amplifiers whose gains are also defined via I2C. The chip contains an alignment help by incorporating 3 rows of 100 conventional Active Pixel Sensors (AI'S) inserted at the top, middle, and lower part of the main photodiode array. The chip has been fabricated in a standard 0.35mm CMOS technology and maximum power consumption is below 30mW.
An EPC class-1 generation-2 baseband processor for passive UHF RFID tag
J.A. Rodríguez-Rodríguez, J. Masuch and M. Delgado-Restituto
Conference · Ph.D. Research in Microelectronics and Electronics PRIME 2009
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Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation-2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35 mu m CMOS technology process and occupies 7mm(2) including pads. The design also incorporates a 10-b rail-to-rail SAR ADC for sensory applications. Under maximum digital activity conditions, post-layout simulations show that the power consumption of the processor below 2.8 mu W.
La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica
A.J. Acosta, R. del Río and A. Rodríguez-Vázquez
Conference · VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2008
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La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a las clases magistrales, experiencias de cátedra, tutorías y clases prácticas, el Trabajo Académicamente Dirigido (TAD) se muestra como altamente eficiente a la hora de trasvasar conocimiento al alumno. En esta comunicación se pone de manifiesto la experiencia de innovación docente puesta en funcionamiento en la Licenciatura en Física de la Universidad de Sevilla y que opera satisfactoriamente desde el curso 2002/03.
Electrical-level synthesis of pipeline ADCs
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
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This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., transistor sizes and biasing conditions. It is based on the combination of a behavioural simulator for performance evaluation, accurate models of the converter components, and an optimization algorithm to minimize the power and area consumption of the circuit solution. The design procedure is herein demonstrated with the complete design of a 0.13 mu m CMOS 10bits@60MS/s pipeline ADC, which only consumes 11.3mW from a 1.2V supply voltage. A close agreement between behavioural- and electrical-level simulations is obtained with only 0.2bit deviation on the measured ENOB.
Data Matrix Code Recognition using the Eye-RIS Vision System
A. Jimenez-Marrufo, A. Mendizabal, S. Morillas-Castillo, R. Dominguez-Castro, S. Espejo, R, Romay-Juarez and A. Rodriguez-Vazquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2007
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This demo illustrates the processing capabilities of the Eye-RIS vision systems; specifically using the Eye-RIS v1.2. These systems employ an AnaFocus's a proprietary architecture where processing is realized in two steps. The first stage of the architecture embeds sensors, parallel processing analog and mixed-signal circuitry, control circuitry and memory. This front-stage is implemented through dedicated bio-inspired chips. The second stage of the Eye-RIS vision system architecture is a digital microprocessor. The combination of parallel preprocessing and serial post-processing makes the Eye-RIS systems very efficient particularly the Eye-RIS systems are capable to close the sensor-processing-actuation loop at a high speed. In this demo, the Eye-RIS v1.2 is used to recognize data matrix codes at more than 200 codes/sec rate.
A 5.3 mW, 2.4 GHz ESD protected low-noise amplifier in a 0.13 um RFCMOS technology
D. Brandano, M. Delgado-Restituto, J. Ruiz-Amaya and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2007
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An Electrostatic Discharge (ESD) protected Low-Noise Amplifier (LNA) for the 2.4GHz ISM band designed in a 0.13 mu m standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8dB power gain, reflexion coeffcients S-11, S-22 <-30dB over the 2.4GHz ISM band, a peak noise figure of 1.8 dB, and an IIP3 of 1dBm, while drawing less than 4.5mA do biasing current from the 1.2V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to +/- 2.0kV, by means of the additional custom protection circuitry.
A 12-bit@40 MS/s Gm-C cascade 3-2 continuous-time sigma-delta modulator
R. Tortosa, A. Aceituno, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2007
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This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade Sigma Delta modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.(dagger 1).
A focal-plane image processor for low power adaptive capture and analysis of the visual stimulus
C.M. Domínguez-Matas, R. Carmona-Galán, F.J. Sánchez-Fernández and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2007
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Portable applications of artificial vision are limited by the fact that conventional processing schemes fail to meet the specifications under a tight power budget. A bio-inspired approach, based in the goal-directed organization of sensory organs found in nature, has been employed to implement a focal-plane image processor for low power vision applications. The prototype contains a multi-layered CNN structure concurrent with 32x32 photosensors with locally programmable integration time for adaptive image capture with on-chip local and global adaptation mechanisms. A more robust and linear multiplier block has been employed to reduce irregular analog wave propagation ought to asymmetric synapses. The predicted computing power per power consumption, 142MOPS/mW, is orders of magnitude above what rendered by conventional architectures.
Integrated circuit interface for artificial skins
R. Maldonado-López, F. Vidal-Verdú, G. Liñán and A. Rodríguez-Vázquez
Conference · Conference on Bioengineered and Bioinspired Systems III, 2007
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Artificial sensitive skins are intended to emulate the human skin to improve the skills of robots and machinery in complex unstructured environments. They are basically smart arrays of pressure sensors. As in the case of artificial retinas, one problem to solve is the management of the huge amount of information that such arrays provide, especially if this information should be used by a central processing unit to implement some control algorithms. An approach to manage such information is to increment the signal processing performed close to the sensor in order to extract the useful information and reduce the errors caused by long wires. This paper proposes the use of voltage to frequency converters to implement a quite straightforward analog to digital conversion as front end interface to digital circuitry in a smart tactile sensor. The circuitry commonly implemented to read out the information from a piezoresistive tactile sensor can be modified to turn it into an array of voltage to frequency converters. This is carried out in this paper, where the feasibility of the idea is shown through simulations and its performance is discussed.
A design tool for high-resolution high-frequency cascade continuous-time sigma delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V Fernández
Conference · Conference on VLSI Circuits and Systems III, 2007
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This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade EA modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Sigma Delta modulator in a 1.2V 130nm CMOS technology.
Tactile retina for slip detection
R. Maldonado López, F. Vidal-Verdú, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference · IEEE International Conference on Virtual Environments, Human-Computer Interfaces and Measurement Systems VECIMS 2006
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The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The array of pressure data provided by these devices can be treated with different image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look at the skin, the information collected by every mechanoreceptor is not sent to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. Something similar happens in the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results illustrated for the case of slip detection, which is certainly demanding in computing requirements. © 2006 IEEE.
Comparison of the DR of continuous time Gm-C filters using different structures
J.F. Fernández-Bootello, M. Delgado-Restituto, A. Rodríguez-Vázquez and D. Brandano
Conference · WSEAS International Conference on CIRCUITS 2006
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This paper presents design techniques to evaluate the noise and distortion of continuous time Gm-C filters. Also presents techniques to improve the dynamic range of such filters keeping a relation of integer numbers between the transconductors. Furthermore the comparison of the dynamic range for the same power using different structures is presented.
A bio-inspired vision front-end chip with spatio-temporal processing and adaptive image capture
C.M. Domínguez-Matas, R. Carmona-Galán, F.J. Sánchez-Fernández, J. Cuadri and A. Rodríguez-Vázquez
Conference · International Workshop on Computer Architecture for Machine Perception and Sensing CAMPS 2006
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This paper presents an advanced CMOS imager with concurrent parallel processing for early-vision tasks. The network is arranged in two layers of 32 x 32 programmable mixed-signal elementary processors with programmable linear feedback and control masks and inter-layer connections for continuous-time cellular neural network dynamics. The ratio of the time constants of these layers is user selectable. There are also feedforward connections to a faster third layer, intended to combine of the outputs of the other two in parallel. We have employed a restricted set of weights' trading flexibility for robustness. It results in a more linear multiplier block and, consequently, a significant reduction of irregularities in the propagation of analog waves ought to asymmetric synapses. Also global and local adaptation to illumination conditions, both throughout the scene and from frame to frame, are implemented on-chip, making use of the available focal-plane processing capabilities. The predicted computing power per area and power consumption is amongst the largest reported, what renders this kind of devices as an efficient front-end for portable applications of artificial vision.
Robust symmetric multiplication for programmable analog VLSI array processing
C. Domínguez-Matas, R. Carmona-Galán, F.J. Sánchez-Fernández and A. Rodríguez-Vázquez
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2006
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This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.
Design of a 1.2-V 130 nm CMOS 13-bit@40 MS/s cascade 2-2-1 continuous-time sigma delta modulator
R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2006
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This paper presents the design of a continuous-time multibit cascade 2-2-1 Sigma Delta modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.
From photons to decisions: The CMOS challenge
A. Rodríguez-Vázquez
Conference · International Workshop on Cellular Nanoscale Networks and their Applications CNNA 2006
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Abstract not available
3-layer CNN chip for focal-plane complex dynamics with adaptive image capture
C.M. Domínguez-Matas, R. Carmona-Galán, F.J. Sánchez-Fernández and A. Rodríguez-Vázquez
Conference · IEEE International Workshop on Cellular Neural Networks and their Applications CNNA 2006
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This paper presents a CMOS implementation of a layered CNN concurrent with 32x32 photosensors with locally programmable integration time for adaptive image capture. The network is arranged in two layers containing feedback and control templates, inter-layer connections and programmable ratio of time constants. There are also feedforward connections to a third layer, which is faster, and devoted exclusively for combining the outputs of the other two. A more robust and linear multiplier block has been employed to reduce irregular analog wave propagation ought to asymmetric synapses. Global and local adaptation circuits are included on-chip. The predicted computing power per power consumption, 240MOPS/mW, is amongst the largest reported, what renders this kind of devices as especially adequate for portable applications of artificial vision.
Design of a 1.2-V cascade continuous-time Sigma triangle modulator for broadband telecommunications
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · International Symposium on Circuits and Systems ISCAS 2006
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This paper presents the design of a continuous-time multibit cascade 2-2-1 Sigma Delta modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 0.13 mu m CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.
Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios
M. Yavari, O. Shwaei and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2006
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This paper presents novel double-sampling cascaded sigma-delta modulator topologies for wideband applications. The proposed modulator structures employ finite impulse response (FIR) noise transfer function (NTF) to achieve the aggressive noise shaping with an additional zero at the half of the sampling frequency to alleviate the quantization noise folding. Cascading of the proposed modulator structures is very simple without any additional circuit requirements.
Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
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This paper presents design considerations for cascade Sigma-Delta Modulators (Sigma Delta Ms) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1(L-2) expandible Sigma Delta M is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach.
Locust-inspired vision system on chip architecture for collision detection in automotive applications
L. Carranza, R. Laviana, S. Vargas, J. Cuadri, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2006
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This paper describes a programmable digital computing architecture dedicated to process information in accordance to the organization and operating principles of the four-layer neuron structure encountered at the visual system of Locusts. This architecture takes advantage of the natural collision detection skills of locusts and is capable of processing images and ascertaining collision threats in real-time automotive scenaRíos. In addition to the Locust features, the architecture embeds a Topological Feature Estimator module to identify and classify objects in collision course.
Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
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This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other one due to the input signal parameters, i.e amplitude and frequency. The latter component, not considered in previous approaches, allows us to accurately predict the resolution loss caused by jitter, showing effects not taken into account up to now in literature which are specially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Time-domain simulations of several modulator topologies intended for VDSL application are given to validate the presented analysis.
Frontiers of CMOS Sigma-Delta Converters - Part2: Continuout-Time Sigma-Delta Converters
A. Rodríguez-Vázquez and J.M. de la Rosa
Conference · European Conference on Circuit Theory and Design ECCTD 2005
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Sigma-delta converters are very well suited for the implementation of analog front-ends in CMOS SoCs. Owing to different advances on both architectures and circuit techniques, these converters are today employed for applications spanning a very wide frequency interval, from instrumentation to telecom. They are clearly dominant in measurement, voice, and audio systems, and coexist with algorithmic, subranging, and pipeline converters in systems for mobile communications and broadband wireline applications like ADSL. Furthermore, it is commonly accepted that whenever an industrial application can be addressed by using a sigma-delta converter, this solution is considered very well suited, for feasibility, yield, robustness, and time-to-market reasons.
During the last few years, significant efforts and contributions have been made to decrease the power budget of sigma-delta converters, to increase their bandwidth and to make them fully compatible with last generation, low-voltage sub-micron technologies. The extended usage of multi-bit quantizers, the emergence of new continuous-time architectures and synthesis techniques, the combination of continuous-time and discrete-time filters, the usage of calibration, the compatibility with very low voltage supplies,... are examples of recent advances on CMOS sigma-delta converter design.
Based on a comprehensive description of sigma-delta operating principles, this tutorial presents an overview of the advances which are currently shaping the field of CMOS sigma-delta converter design. Topics covered in the tutorial include the following: New architectures and optimization techniques for wideband discrete-time sigma-delta modulators. New synthesis techniques and architectures for continuous-time sigma-delta modulators. Continuous-time, discrete-time hybrid architectures. New sigma-delta and hybrid converter architecture: parallel, time-interleaved, sigma-delta pipeline,... Calibration techniques. Strategies for multi-mode and multi-standard transceivers. Low-voltage, low-power design. Deep-submicron design.
Design Considerations for Multistandard Cascade ΣΔ Modulators
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
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This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.
An approach to the design of the design of multistandard ΣΔ modulators
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · WSEAS Int. Conf. on Electronics, Control and Signal Processing ICECS 2005
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This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture-and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach.
A CMOS High-Resolution Automotive Sensor A/D Interface Based on a 110-dB @ 40kS/s Programmable-Gain Cascade 2-1 Sigma-Delta Modulator with Embedded Design-for-Testability Strategies
J.M. de la Rosa, S. Escalera, O. Guerra, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
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Abstract not available
Vehículo-Robot para aplicaciones de Control y Visión Artificial
L. Carranza-González, E. Roca-Moreno and A. Rodríguez-Vázquez
Conference · V Jornadas de Computación Reconfigurable y Aplicaciones CEDI 2005
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Este trabajo presenta el diseño del vehículo-robot LRC-1, ideado para aplicaciones de control y visión en tiempo real. El LRC-1 está compuesto por sistemas electrónicos y mecánicos. Los sistemas electrónicos se han basado en un microcontrolador, circuitería de control, adquisición de datos y cómputo sintetizada en lógica reconfigurable, un subsistema de comunicaciones bidireccional de radiofrecuencia, una cámara de vídeo y un transmisor de microondas. Las aplicaciones del robot son generales y actualmente se está usando como plataforma para el desarrollo de un SoC sensor-procesador para automoción. Con esa finalidad, en fase de
descripción HDL se encuentran una unidad de detección temprana de colisiones inspirada en el sistema
de visión del insecto langosta (Locusta migratoria) y un clasificador topológico-estadístico de objetos que en breve estarán sintetizados en lógica reconfigurable formando parte del LRC-1, junto con un sensor de imágenes CMOS de gran rango dinámico diseñado en el IMSE-CNM. Por otra parte, el sistema mecánico está compuesto por un motor eléctrico, un sistema de tracción diferencial y servomecanismos. El robot puede operar básicamente en tres modos: control manual, control automático gobernado por un ordenador y modo
autónomo.
Dynamic range optimization of continuous-time G(m)-C filters
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2005
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This paper presents a fast procedure for the system-levcl evaluation of noise and distortion in continuous-time G(m)-C filters. The presented approach is based on Volterra's series expansion and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of filters while keeping the area and power consumption at a minimum. A seventh-order, elliptic, G(m)-C low-pass filter, realized in a 0.18 mu m CMOS technology, following the proposed procedure, demonstrates the suitability of the approach.
A reuse-based framework for the design of analog and mixed-signal ICs
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.
Continuous-time cascaded delta sigma modulators for VDSL: A comparative study
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · Conference on VLSI Circuits and Systems II, 2005
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This paper describes new cascaded continuous-time Sigma Delta modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely: transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.
A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 sigma delta modulator with programmable gain and programmable chopper stabilization
O. Guerra, S. Escalera, J.M. de la Rosa, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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This paper describes a 0.35 μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/ 2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40 degrees C, 175 degrees C). The modulator architecture has been selected after an exhaustive comparison among multiple Sigma Delta M topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of the filter while keeping the area and power consumption at a minimum. The proposed approach is demonstrated with the design, from system- to physical-level, of a seventh-order low-pass continuous-time elliptic filter for a high-performance broadband power-line communication receiver. The filter shows a nominal cut-off frequency of f(c) = 34MHz, less than 1 dB ripple in the pass-band, and a maximum stop-band rejection of 65 dB. Additionally, the filter features 12 dB programmable boost in the pass-band to counteract high frequency components attenuation. Taking into account its wideband transfer characteristic, the filter has been implemented using G(m)-C techniques. The basic building block of its structure, the transconductor, uses a source degeneration topology with local feedback for linearity improving and shows a worst-case intermodulation distortion of -70 dB for two tones close to the passband edge, separated by 1 MHz, with 70mV of amplitude. The filter combines very low noise (peak root spectral noise density below 56nV/root Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5V(pp) amplitude) properties. The filter has been designed in a 0.18 mu m CMOS technology and it is compliant with industrial operation conditions (40 to 85 degrees C temperature variation and 5% power supply deviation). The filter occupies 13 mm(2) and exhibits a typical power consumption of 450 mW from a 1.8V voltage supply.
Simulation-based high-level synthesis of nyquist-rate data converters using MATLAB/SIMULINK
J. Ruiz-Amaya, J.M. de la Rosa, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB (R). The embedded simulator uses SIMULINK (R) C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK (R) elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK (R) platform by using the MATLAB (R) engine library, so that the optimization core runs in background while MATLAB (R) acts as a computation engine. The implementation on the MATLAB (R) platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13 mu m CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.
Geometrically-constrained, parasitic-aware synthesis of analog ICs
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very timeconsuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenaRío is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.
On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.
ACE16k based stand-alone system for real-time pre-processing tasks
L. Carranza, F. Jiménez Garrido, G. Liñán-Cembrano, E. Roca, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
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This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.
Macromodelling for analog design and robustness boosting in bio-inspired computing models
J. Cuadri, G. Liñán and A. Rodríguez-Vázquez
Conference · Conference on Bioengineered and Bioinspired Systems II, 2005
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Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads to a netlist of more than 100.000 nodes for a small array of 100x150 pixels. Moreover, introducing an optical input in the low level simulation is nowadays not feasible with standard electrical simulation environments. Given that, to accomplish the task of integrating those systems in silicon to build compact, low power consuming, and reliable systems, a previous step in the standard analog electronic design flux should be introduced. Here a methodology to make the translation from the biological model to circuit-level specifications for electronic design is proposed. The purpose is to include non ideal effects as mismatching, noise, leakages, supply degradation, feedthrough, and temperature of operation in a high level description of the implementation, in order to accomplish behavioural simulations that require less computational effort and resources. A particular case study is presented, the analog electronic implementation of the locust's Lobula Giant Movement Detector (LGMD), a neural structure that fires a collision alarm based on visual information. The final goal is a collision threat detection vision system on-chip for automotive applications.
Tactile on-chip pre-processing with techniques from artificial retinas
R. Maldonado-López, F. Vidal-Verdú, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference · Conference on Bioengineered and Bioinspired Systems II, 2005
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The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide can be managed with many image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look to the skin, the information collected by every mechanoreceptor is not carried to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. This is also the behavior of the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results when it faces the detection of the slip, which involves fast real-time processing.
A direct synthesis method of cascaded continuous-time sigma-delta modulators
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
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This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to place the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealifies.(dagger 1)
A 0.18 μm CMOS low-noise elliptic low-pass continuous-time filter
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
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This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band to counteract high frequency components attenuation. The filter shows a nominal cutoff frequency of f(c) = 34 MHz, less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. The filter also exhibits low noise feature (peak root spectral noise density below 56nV/root Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5V(pp) amplitude). It has been designed in a 0.18 mu m CMOS technology and it is compliant with industrial operation conditions (40 to 85 degrees C temperature variation and +/- 5% power supply deviation). Simulations show a typical power consumption of 450 mW @ 1.8V supply.
Analysis of clock jitter error in multibit continuous-time sigma delta modulators with NRZ feedback waveform
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
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This paper presents a detailed study of the clock jitter error in multibit continuous-time Sigma Delta modulators with non-return-to-zero feedback waveform. Closed-form expressions are derived for the in-band error power and the signal-to-noise ratio showing that the jitter-induced noise can be separated into two main components: one depending on the modulator loop filter and the other one due to the input signal. The latter, not considered in previous approaches, allows us to accurately predict the signal-to-noise ratio degradation and to optimize the modulator performance in terms of jitter insensitivity. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascaded or single-loop architectures. Time-domain simulations of several modulators are shown to validate the presented approach.(dagger 1)
An embedded 12-bit 80 MS/s A/D/A interface for power-line communications in 0.13 um pure digital CMOS technology
M. Delgado-Restituto, J. Ruiz-Amaya, J.M. de la Rosa, J.F. Fernández-Bootello, L. Díez, R. del Río and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
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This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13 mu m pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band powerline communications. The A/D converter uses a pipelined structure, whereas the D/A stage is based on segmented current steering techniques. In both cases, specifications are 12-b resolution at 80MS/s and MTPR above 56dB.
Behavioral modeling simulation and high-level synthesis of pipeline A/D converters
J. Ruiz-Amaya, J.M. de la Rosa, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
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This paper presents a MATLAB (R) toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital converters. SIMULINK (R) C-coded S-functions are used to describe the behavioral models of all building blocks, including their main circuit errors. This approach significantly speeds up system-level simulations while keeping high accuracy - verified with HSPICE - and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable CAD tool for the high-level design of broadband communication analog front-ends. As a case study, an embedded 0.13 mu m CMOS 12bit@80MS/s A/D interface for a PLC chipset is designed to show the capabilities of the presented tool.(dagger 1)
Architectures and design considerations for wireline sigma delta modulators beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Workshop on ADC Modelling and Testing IWADC 2005
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In this paper we discuss design considerations for sigma-delta modulators (&USigma;&UDelta; Ms) aimed at high-linearity highspeed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12-15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenaRío. We show that, after proper architecture selection, guided by a simple power estimation method, these &USigma;&UDelta; Ms are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μ m CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade &USigma;&UDelta; Ms to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results. © 2005 Elsevier Ltd. All rights reserved.
A New Method for the High-Level Synthesis of Continuous-Time Cascaded ΣΔ Modulators
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2004
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This paper presents an efficient method to design cascaded ΣΔ modulators implemented with continuous-time circuits. Instead of using a discrete-to-continuous time transformation, the proposed methodology is based on the direct synthesis of the whole cascaded architecture. This leads to more efficient topologies in terms of circuit complexity, power consumption and robustness with respect to parasitics. As an application, new cascaded topologies are synthesized and optimized to cope with VDSL specifications.
Experimental Characterization of an Integrated Chaos-Based FM-DCSK Transmitter Chipset
M. Delgado-Restituto, A.J. Acosta-Jimenez and A. Rodriguez Vazquez
Conference · Experimental Chaos Conference 2004
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Abstract not avaliable
A mixed-signal ASIC for FM-DCSK modulation
M. Delgado-Restituto, A.J. Acosta-Jimenez and A. Rodriguez-Vazquez
Conference · Design of Circuits and Integrated Systems Conference DCIS 2004
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This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER =10(-3) for Eb/No lower than 28 dB.
ACE16k-Ds: un Sistema autónomo programable para el preprocesamiento de imágenes en tiempo real
L. Carranza-González, F.J. Jimenez-Garrido, G. Liñán-Cembrano, E. Roca-Moreno, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2004
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Este artículo describe un sistema electrónico autónomo y programable, denominado ACE16k-DS, que permite sensar y procesar imágenes en tiempo real. La arquitectura del sistema está basada en el chip ACE16k y en la FPGA Xc4028xl de Xilinx en la que se han sintetizado una Unidad de Control Programable de propósito específico y un generador de vídeo digital. Las imágenes son sensadas y procesadas, en modo analógico, en el chip ACE16k, siguiendo instrucciones secuenciadas por la Unidad de Control Programable. El generador de vídeo digital permite visualizar, en una pantalla TFT, las imágenes procesadas en tiempo real.
A neural model of the locust visual system for detection of object approaches with real-world scenes
M.S. Keil, E. Roca-Moreno and A. Rodríguez-Vázquez
Conference · International Conference on Visualization, Imaging, and Image Processing VIIP 2004
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In the central nervous systems of animals like pigeons and locusts, neurons were identified which signal objects approaching the animal on a direct collision course. Unraveling the neural circuitry for collision avoidance, and identifying the underlying computational principles, is promising for building vision-based neuromorphic architectures, which in the near future could find applications in cars or planes. At the present there is no published model available for robust detection of approaching objects under real-world conditions. Here we present a computational architecture for signalling impending collisions, based on known anatomical data of the locust lobula giant movement detector (LGMD) neuron. Our model shows robust performance even in adverse situations, such as with approaching low-contrast objects, or with highly textured and moving backgrounds. We furthermore discuss which components need to be added to our model to convert it into a full-fledged real-world-environment collision detector.
A mixed-signal integrated circuit for FM-DCSK modulation
M. Delgado-Restituto, A.J. Acosta and A. Rodríguez-Vázquez
Conference · European Solid-State Circuits Conference ESSCIRC 2004
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This paper presents a mixed-signal ASIC for a Frequency-Modulated Differential Chaos Shift Keying (FM-DCSK) communication system [1][2] which has been implemented in a 2P-3M 0.35mum CMOS technology. The prototype has been provided with several programming capabilities to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme. The operation of the integrated circuit is herein illustrated for a data rate of 500kb/s and a transmission bandwidth in the range of 17MHz. Based on experimental results, an estimation of the Bit Error Rate (BER) performance of the modulation scheme in a wireless environment at the 2.4GHz ISM band under different propagation conditions has been realized. Measured results confirm theoretical predictions.(dagger)
MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time sigma delta modulators
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, E. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
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This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of SigmaDelta Modulators (SigmaDeltaMs). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for SigmaDeltaM synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.
A 0.35 μm CMOS 17-bit@40 kS/s sensor A/D interface based on a programmable-gain cascade 2-1 sigma delta modulator
J.M. García-González, S. Escalera, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
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This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35mum standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) SigmaDelta modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from muVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.
An alternative DFT methodology to test high-resolution sigma delta modulators
S. Escalera, J.M. García-González, O. Guerra, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2004
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In this paper, a novel DfT methodology to test high-resolution SigmaDelta Modulators (SigmaDeltaM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma delta modulators in the MATLAB/SIMULINK environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
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This paper presents a MATLAB toolbox for the automated high-level sizing of SigmaDelta Modulators (SigmaDeltaMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.)
A CNN-driven locally adaptive CMOS image sensor
R. Carmona, C.M. Domínguez-Matas, J. Cuadri, F. Jiménez-Garrido and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
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A bioinspired model for mixed-signal array mimics the way in which images are processed in the visual pathway. Focal-plane processing of images permits local adaptation of photoreceptor structures in silicon. Beyond simple resistive grid filtering, nonlinear and anisotropic diffusion can be programmed in this CNN chip. This paper presents the local circuitry for sensors adaptation based on the mixed-signal VLSI parallel processing infrastructure in CMOS.
Challenges and opportunities for analog neural processing in the deep submicron SoC era
A. Rodríguez-Vázquez
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2004
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Abstract not available
A 1000 FPS@128x128 vision processor with 8-bit digitized I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference · European Solid-State Circuits Conference ESSCIRC 2004
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This paper presents a mixed-signal programmable, chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-mum fully digital CMOS technology, contains similar to 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm(2) and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be: programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions - applications using exposures of about 50 mus have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory) and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.
Bio-inspired nano-sensor-enhanced CNN visual computer
W. Porod, F. Werblin, L.O. Chua, T. Roska, A. Rodríguez-Vázquez, B. Roska, P. Fay, G.H. Bernstein, Y.F. Huang A.I. Csurgay
Conference · Conference on Converging Technologies for Improving Human Performance NBIC 2004
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Nanotechnology opens new ways to utilize recent discoveries in biological image processing by translating the underlying functional concepts into the design of CNN (cellular neural/nonlinear network)-based systems incorporating nanoelectronic devices. There is a natural intersection joining studies of retinal processing, spatio-temporal nonlinear dynamics embodied in CNN, and the possibility of miniaturizing the technology through nanotechnology. This intersection serves as the springboard for our multidisciplinary project. Biological feature and motion detectors map directly into the spatio-temporal dynamics of CNN for target recognition, image stabilization, and tracking. The neural interactions underlying color processing will drive the development of nanoscale multispectral sensor arrays for image fusion. Implementing such nanoscale sensors on a CNN platform will allow the implementation of device feedback control, a hallmark of biological sensory systems. These biologically inspired CNN subroutines are incorporated into the new world of analog-and-logic algorithms and software, containing also many other active-wave computing mechanisms, including nature-inspired (physics and chemistry) as well as PDE-based sophisticated spatio-temporal algorithms. Our goal is to design and develop several miniature prototype devices for target detection, navigation, tracking, and robotics. This paper presents an example illustrating the synergies emerging from the convergence of nanotechnology, biotechnology, and information and cognitive science.
SIMSIDES Toolbox: An Interactive Tool for the Behavioural Simulation of Discrete- and Continuous-time ΣΔ Modulators in the MATLAB/SIMULINK Environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, R. del Río, B. Moreno-Reina, B. Pérez-Verdú, R. Tortosa, R. Romay and A. Rodríguez-Vázquez
Conference · Design of Circuits and Integrated Systems Conf. DCIS 2003
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This paper presents an user-friendly tool, named SIMSIDES, for the time-domain simulation of ΣΔ modulators in the MATLAB/SIMULINK environment. The tool is able to simulate an arbitrary ΣΔ topology implemented by using discrete-time - switched-capacitor and switched-current - and continuous-time circuit techniques, considering the most important circuit parasitics. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions. The combination of high accuracy, short CPU-time and interoperability of different circuit models, make the tool into a valuable instrument to optimize the design of ΣΔ analog-to-digital converters.
Design and Implementation of a 0.35μm CMOS Programmable-Gain 2-1 Cascade ΣΔ Modulator for Automotive Sensors
J.M. García-González, S. Escalera, J.M. de la Rosa, F. Medeiro, R. del Río, O. Guerra, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2003
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Abstract not available
Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Forum on Specification & Design Languages FDL 2003
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Abstract not available
Design Considerations for ΣΔ Modulators Beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop IBERCHIP 2003
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In this paper we discuss design considerations for Sigma-Delta modulators (ΣΔM) aimed at high-linearity, high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range 12-15bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade multi-bit architec-tures in a low-voltage, deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are still promising candidates to achieve post-ADSL performances in coming CMOS processes.
Behavioural modelling and simulation of sigma delta modulators using hardware description languages
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2003
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Behavioural simulation is the common alternative to the costly electrical simulation of SigmaDelta modulators (EAMs). This paper explores the behavioural modelling and simulation of SigmaDeltaMs by using hardware description languages (HDLs) and commercial behavioural simulators,, as an alternative to the common special-purpose behavioural simulators. A library of building blocks, where a HDL has been used to model a complete set of circuit non-idealities influencing the performance of SigmaAMs, is introduced. Three alternatives for introducing SigmaDeltaM topologies have been implemented Experimental results of the simulation of a fourth-order 2-1-1 cascade multi-bit YAM are given.
A 2.5-V CMOS wideband sigma-delta modulator
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE Instrumentation and Measurement Technology Conference I2MTC 2003
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A high-performance SigmaDelta modulator for wireline communication applications is presented It employs a 4th-order cascade multi-bit architecture that requires only 16 oversampling ratio, and has been implemented using fully-differential SC circuits in a 0.25-mum CMOS technology. Measurements show a dynamic range of 84dB operating at Z2MS/s output rate, and 79dB at 4.4MS/s. The whole prototype dissipates 65.8mW from a 2.5-V supply.
Expandible high-order cascade Sigma Delta modulator with constant, reduced systematic loss of resolution
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Instrumentation and Measurement Technology Conference I2MTC 2003
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An arbitrary order sigma-delta modulator cascade architecture is presented with only 1-bit loss of resolution due to scaling issues, even with single-bit quantization. This loss is kept with a high overloading point, regardless of the order. Simulations reveal that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization.
Programmable retinal dynamics in a CMOS mixed-signal array processor chip
R. Carmona, F. Jiménez-Garrido, R. Domiguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference · Conference on Bioengineered and Bioinspired Systems 2003
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The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5mum CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 x 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.
Towards a computational approach for collision avoidance with real-world scenes
M.S. Keil and A. Rodríguez-Vázquez
Conference · Conference on Bioengineered and Bioinspired Systems 2003
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In the central nervous systems of animals like pigeons and locusts, neurons were identified which signal objects approaching the animal on a direct collision course. In order to timely initiate escape behavior, these neurons must recognize a possible approach (or at least differentiate it from similar but non-threatening situations), and estimate the time-to-collision (ttc). Unraveling the neural circuitry for collision avoidance, and identifying the underlying computational principles, should thus be promising for building vision-based neuromorphic architectures, which in the near future could find applications in cars or planes. Unfortunately, a corresponding computational architecture which is able to handle real-situations (e.g. moving backgrounds, different lighting conditions) is still not available (successful collision avoidance of a robot was demonstrated only for a closed environment). Here we present two computational models for signalling impending collision. These models are parsimonious since they possess only the minimum number of computational units which are essential to reproduce corresponding biological data. Our models show robust performance in adverse situations, such as with approaching low-contrast objects, or with highly textured backgrounds:. Furthermore, a condition is proposed under which the responses of our models match the so-called eta-function. We finally discuss which components need to be added to our model to convert it into a full-fledged real-world-environment collision detector.
On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line.
S. Escalera, C.M. Domínguez-Matas, J.M. García-González, O. Guerra and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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This paper presents a CMOS 0,6mum, mixed-signal MODEM ASIC for data transmission on the low-voltage power line. The circuit includes all the analog circuitry needed for input interfacing and modulation/demodulation (PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, decision circuitry, etc.) plus the logic circuitry needed for control purposes. The circuit operates correctly in the whole industrial temperature range, from -45 to 80degreesC, under 5% variations of the 3.3V supply voltage.
Analog weight buffering strategy for CNN chips
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Carmona, S. Espejo and R. Domínguez Castro
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, accuracy is ultimately limited by the controlling signals. This paper presents a buffering strategy intended to achieve 8-bit equivalent accuracy in the distribution of the internal analog signals, as employed in the chips ACE4k [1], ACE16k [2], and CACE1k [3].
Design considerations for an automotive sensor interface sigma delta modulator
F. Medeiro, J.M. de la Rosa, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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In this paper we discuss design considerations for a Sigma-Delta modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. This SigmaDeltaM contains a programmable-gain input interface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently implemented by proper architecture selection and ad hoc sampling and integration capacitor structures. Behavioral simulations of a 17bit 40kS/s modulators are included to illustrate the design considerations.
A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time sigma delta modulators
J. Moreno-Reina, J.M. de la Rosa, F. Medeiro, R. Romay, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of SigmaDelta modulators implemented by using switched-capacitor, switched-current and continuous-time Circuits, considering the most important error mechanisms. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions-The outcome is a complete SIMULINK block library that allows interactive, fast and accurate simulation of an arbitrary SigmaDelta topology.
Accurate VHDL-based simulation of sigma delta modulators
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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Computational cost of transient simulation of SigmaDelta modulators (SigmaDeltaMs) at the electrical level is prohibitively high. Behavioral simulation techniques arise as a promising solution to this problem. This paper demonstrates that both, hardware description languages (HDLs) and commercial HDL simulators, constitute a valuable alternative to traditional special-purpose SigmaDelta behavioral simulators. In this sense, a library of HDL building blocks, modeling a complete set of circuit non-idealities which influence the performance of SigmaDeltaMs, is presented. With these blocks, SigmaDeltaM architectures can be described in two different ways, which are analyzed in detail. Experimental results are provided through several simulations of a fourth-order 2-1-1 cascade multi-bit SigmaDeltaM.
A versatile sensor interface for programmable vision systems-on-chip
A. Rodríguez-Vázquez, G. Liñán, E. Roca, S. Espejo and R. Dominguez-Castro
Conference · Conf. on Sensors and Camera Systems for Scientific, Industrial, and Digital Photography 2003
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This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35mum n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 x 128 identical cells, each cell corresponding to a pixel. Die size is 11.885 x 12.230mm(2) and cell size is 75.7mum x 73.3mum. Each cell contains 198 transistors dedicated to functions like processing, storage, and sensing. The system is oriented to real-time, single-chip image acquisition and processing. Since each pixel performs the basic functions of sensing, processing and storage, data transferences are fully parallel (image-wide). The programmability of the processing functions enables the realization of complex image processing functions based on the sequential application of simpler operations. This paper provides a general overview of the system architecture and functionality, with special emphasis on the optical interface.
CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using the low-voltage power-line
S. Escalera, C.M. Domínguez-Matas, J.M. García-González, O. Guerra and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
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This paper presents a CMOS 0.6mum mixed-signal MODEM ASIC for data transmission using the low-voltage power line. This circuit includes all the analog blocks needed for input interfacing and modulation/demodulation (PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, and decision circuitry) plus the logic circuitry needed for control purposes. The circuit operates correctly within the industrial temperature range, from -45 to 80 degreesC, under 5% variations of the 3.3V supply voltage.
System-level optimization of baseband filters for communication applications
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
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In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power/area consumptions is presented. The proposed approach relies on building programming circuit elements as arrays of switchable unit cells and defines the synthesis as a constrained optimization problem with both continuous and discrete variables, this last rep-resenting the number of enabled cells of the arrays at each configuration. The cost function under optimization is; then, defined as a weighted combination of performance indices which are estimated from macromodels of the circuit elements. The methodology has been implemented in MATLAB(TM) and C++, and covers all the classical approximation techniques for filters, most common circuit topologies (namely, ladder simulation and cascaded biquad realizations) and both transconductance-C (G(m)-C) and active-RC implementation approaches. The proposed synthesis strategy is illustrated with a programmable equal-ripple ladder G(m)-C filter for a multi-band power-line communication modem.
A sigma delta modulator for a programmable-gain, low-power, high-linearity automotive sensor interface
J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
resumen
This paper describes the design and electrical implementation of a 0.351mum CMOS 17-bit@40kS/s Sigma-Delta Modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. First of all, the paper discusses the most important limiting factors and design considerations applicable to a high-resolution SigmaDeltaM for sensor interfaces. After an exhaustive comparison among multiple SigmaDeltaM architectures in terms of resolution, speed and power dissipation, a third-order (2-1) cascade SigmaDeltaM is chosen. For a better fitting to the characteristics of different sensor outputs, the SigmaDeltaM here includes a programmable set of gains (0.5, 1, 2, and 4). The gain programmability is implemented by a reconfigurable capacitor array of unitary capacitors. In order to relax the amplifier dynamics requirements for the different modulator gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. Behavioural simulations considering transistor-level circuit parasitics shows a Dynamic Range (DR.) over 105dB for all cases of the modulator gain.
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Domiguez-Castro and S. Espejo
Conference · Conference on VLSI Circuits and Systems 2003
resumen
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35mum standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.
Mismatch-induced trade-offs and scalability of analog preprocessing visual microprocessor chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
resumen
This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range. The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenaRíos, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.
A 79-dB 4.4MS/s ΣΔ Modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2002
resumen
Abstract not available
Design of a broadband ΣΔ modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen
Abstract not available
Generation of technology-portable flexible analog blocks
R. Castro-López, F.V. Fernández, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even to different technology processes. By careful integration of the tuning process of design parameters with layout generation, fully functional designs are generated in a few minutes of CPU time.
A 2.5-V sigma delta modulator in 0.25μm CMOS for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
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This paper presents a dual-quantization cascade SC SigmaDelta modulator intended for A/D conversion in ADSL applications. The modulator combines a low oversampling ratio with 3-bit resolution in the last stage, to achieve 14bit@4.4MS/s (16x) and 15bit@2.2MS/s (32x) with no need of correction/calibration mechanisms. It consumes 66mW from a single 2.5-V supply and has been implemented in 0.25-mum CMOS technology.
A processing element architecture for high-density focal plane analog programmable array processors
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
The architecture of the elementary Processing Element - PE- used in a recently designed 128x128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 x 3 convolution masks. The vision chip has been implemented in a standard 0.35mum CMOS technology. The main PE related figures are: 180 cells/mm(2), 18 MOPS/cell; and 180 muW/cell.
Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
This paper explores different trade-offs associated to the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of processors), as fabrication technologies scale down into deep sub-micron.
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5mum CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper.
Bio-inspired analog VLSI design realizes programmable complex spatio-temporal dynamics on a single chip
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed in 0.5 mum CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper.
Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop on Advances in Analog Circuit Design AACD 2002
resumen
This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-mum CMOS technology are given and illustrated through experimental results.
CE16K: A 128x128 focal plane analog processor with digital I/O.
G. Liñán, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference · IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
resumen
This paper presents a new generation 128x128 Focal-Plane. Analog Programmable Array Processor FPAPAP-, from a system level perspective, which has been manufactured in a 0.35mum standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy -8b-requirements of most real time -early-vision processing applications. It is easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 90% of them working in analog mode, and exhibits a relatively low power consumption -<4W, i.e. less than 1muW per transistor. Computing vs. power peak values are in the order of 1TeraOPS/W, while maintained VGA processing throughputs of 100Frames/s are possible with about 10-20 basic image processing tasks on each frame.
CMOS realization of a 2-layer CNN universal machine chip
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference · IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
resumen
Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the possibilities of these complex spatio-temporal dynamics in image processing, a prototype chip has been developed implementing this CNN model with analog signal processing blocks. This chip has been designed in a 0.5 mum CMOS technology. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper(a).
CMOS design of cellular APAPs and FPAPAPs: An overview
A. Rodríguez-Vázquez
Conference · IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
resumen
Abstract not available
A multimode gray-scale CMOS optical sensor for Visual computers
G. Liñán, A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro and E. Roca
Conference · IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
resumen
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as well as the mechanism for transducing the photogenerated charges into the correspondent pixel voltage. Both linear or logarithmic compression acquisition modes are available. This makes the sensor very suitable to be used in very different illumination conditions.
A symbolic pole/zero extraction methodology based on analysis of circuit time-constants
O. Guerra, J.D. Rodríguez-García, F.V. Fernández and A. Rodríguez-Vázquez
Conference · International Workshop on Symbolic Methods and Applications to Circuit Design SMACD 2002
resumen
This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.
Libros
Visual Inference for IoT Systems: A Practical Approach
D. Velasco-Montero, J. Fernández-Berni and A. Rodríguez-Vázquez
Book · 145 p, 2022
resumen
link
This book presents a systematic approach to the implementation of Internet of Things (IoT) devices achieving visual inference through deep neural networks. Practical aspects are covered, with a focus on providing guidelines to optimally select hardware and software components as well as network architectures according to prescribed application requirements.
The monograph includes a remarkable set of experimental results and functional procedures supporting the theoretical concepts and methodologies introduced. A case study on animal recognition based on smart camera traps is also presented and thoroughly analyzed. In this case study, different system alternatives are explored and a particular realization is completely developed.
Illustrations, numerous plots from simulations and experiments, and supporting information in the form of charts and tables make Visual Inference and IoT Systems: A Practical Approach a clear and detailed guide to the topic. It will be of interest to researchers, industrial practitioners, and graduate students in the fields of computer vision and IoT.
Low-power smart imagers for vision-enabled sensor networks
J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Book · 156 p, 2012
resumen
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This book presents a comprehensive, systematic approach to the development of vision system architectures that employ sensory-processing concurrency and parallel processing to meet the autonomy challenges posed by a variety of safety and surveillance applications. Coverage includes a thorough analysis of resistive diffusion networks embedded within an image sensor array. This analysis supports a systematic approach to the design of spatial image filters and their implementation as vision chips in CMOS technology. The book also addresses system-level considerations pertaining to the embedding of these vision chips into vision-enabled wireless sensor networks. Describes a system-level approach for designing of vision devices and embedding them into vision-enabled, wireless sensor networks; Surveys state-of-the-art, vision-enabled WSN nodes; Includes details of specifications and challenges of vision-enabled WSNs; Explains architectures for low-energy CMOS vision chips with embedded, programmable spatial filtering capabilities; Includes considerations pertaining to the integration of vision chips into off-the-shelf WSN platforms.
Device-level modeling and synthesis of high-performance pipeline ADCs
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Book · 209 p, 2011
resumen
link
This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.
Reuse-Based Methodologies And Tools in the Design of Analog and Mixed-Signal Integrated Circuits
R. Castro-López, F.V. Fernández-Fernández, O. Guerra-Vinuesa and A. Rodríguez-Vázquez
Book · 393 p, 2006
resumen
link
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moore Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design -more subtle, hierarchically loose, and handicraft-demanding- has hindered a similar level of consensus and development.
Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks.
Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance.
CMOS cascade sigma-delta modulators for sensors and telecom. Error analysis and practical design
R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez
Book · ACSP, 299 p, 2006
resumen
link pdf
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures.
The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks.
The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors.
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.
CMOS Telecom Data Converters
A. Rodríguez-Vázquez, F. Medeiro-Hidalgo and E. Janssens (Eds.)
Book · 588 p, 2003
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CMOS Telecom Data Converters compiles the latest achievements regarding the design of high-speed and high-resolution data converters in deep submicron CMOS technologies. The four types of analog-to-digital converter architectures commonly found in this arena are covered, namely sigma-delta, pipeline, folding/interpolating and flash. For all these types, latest achievements regarding the solution of critical architectural and circuital issues are presented, and illustrated through IC prototypes with measured state-of-the-art performances. Some of these prototypes are conceived to be employed at the chipset of newest generation wireline modems (ADSL and ADSL+). Others are intended for wireless transceivers. Besides analog-to-digital converters, the book also covers other functions needed for communication systems, such as digital-to-analog converters, analog filters, programmable gain amplifiers, digital filters, and line drivers.
Systematic design of CMOS switched-current bandpass sigma-delta modulators for digital communication chips
J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez (Eds.)
Book · 499 p, 2002
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Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips gives a systematic methodology for designing Sigma-Delta Modulators (Sigma-Delta Ms), specially those of the bandpass type, realized in digital CMOS technologies by using switched-current (SI) circuits. For this purpose, an analysis of SI error mechanisms as well as their influence on the performance of Sigma-Delta Ms is presented in a detailed and comprehensive style. On the one hand, the depth of such an analysis allows designers to get practical knowledge of the performance degradation of SI Sigma-Delta Ms through closed-form expressions that relate the modulator specifications to SI cell design parameters. On the other hand, the behavioural models derived from that study make it possible a fast and precise time-domain simulation of SI Sigma-Delta Ms, shown in the book through a simulator developed in MATLAB/SIMULINK. The architectures and circuit design methodologies presented in this book are demonstrated through two standard CMOS IC prototypes - the first silicon realizations of SI bandpass Sigma-Delta Ms - intended for AM digital radio receivers. The good performance comparison obtained with current state-of-the-art of switched-capacitor ICs demonstrates the viability of SI circuits for the realization of digital communication chips. Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips is organized such that it can be useful for a large audience: from novices in the field to experienced Sigma-Delta M designers. The comprehensive treatment of SI Sigma-Delta Ms given in this book will allow all of them to improve their productivity through the incorporation of circuit knowledge and CAD tools to optimize the design and to shorten the design cycle.
Capítulos de libros
ADCs for Image Sensors: Review and Performance Analysis
Juan A. Leñero-Bardallo and Angel Rodríguez-Vázquez
Book Chapter · Analog Electronics for Radiation Detection, pp 47-70, 2016
resumen
Abstract not avaliable
Image feature extraction acceleration
J. Fernández-Berni, M. Suárez-Cambre, R. Carmona-Galán, V. Brea, R. del Río, D. Cabello and Á. Rodríguez-Vázquez
Book Chapter · Image Feature Detectors and Descriptors, SCI, vol. 630, pp 109-132, 2016
resumen
doi pdf
Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of dealing with individual pixels at the earliest processing levels. In this regard, conventional system architectures do not take advantage of potential exploitation of parallelism and distributed memory from the very beginning of the processing chain. Raw pixel values provided by the front-end image sensor are squeezed into a high-speed interface with the rest of system components. Only then, after deserializing this massive dataflow, parallelism, if any, is exploited. This chapter introduces a rather different approach from an architectural point of view. We present two Application-Specific Integrated Circuits (ASICs) where the 2-D array of photo-sensitive devices featured by regular imagers is combined with distributed memory supporting concurrent processing. Custom circuitry is added per pixel in order to accelerate image feature extraction right at the focal plane. Specifically, the proposed sensing-processing chips aim at the acceleration of two flagships algorithms within the computer vision community: the Viola-Jones face detection algorithm and the Scale Invariant Feature Transform (SIFT). Experimental results prove the feasibility and benefits of this architectural solution.
A focal plane processor for continuous-time 1-D optical correlation applications
G. Liñán-Cembrano, L. Carranza, B. Alexandre, A. Rodríguez-Vázquez, P. de la Fuente and T. Morlanes
Book Chapter · Focal-Plane Sensor-Processor Chips, pp 151-179, 2011
resumen
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This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation applications. The chip contains 200 sensory processing elements, which acquire light patterns through a 2mm×10.9μm photodiode. The photogenerated current is scaled at the pixel level by five independent 3-bit programmable-gain current scaling blocks. The correlation patterns are defined as five sets of two hundred 3-bit numbers (from 0 to 7), which are provided to the chip through a standard I2C interface. Correlation outputs are provided in current form through 8-bit programmable gain amplifiers (PGA), whose configurations are also defined via I2C. The chip contains a mounting alignment help, which consists of three rows of 100 conventional active pixel sensors (APS) inserted at the top, middle and bottom part of the main photodiode array. The chip has been fabricated in a standard 0.35μm CMOS technology and its maximum power consumption is below 30mW. Experimental results demonstrate that the chip is able to process interference patterns moving at an equivalent frequency of 500kHz.
A low-power baseband processor for passive RFID tags employing low-power design techniques
J.A. Rodríguez-Rodríguez and M. Delgado-Restituto
Book Chapter · Advances in RFID Tags, 2011
resumen
This chapter focuses on the design of the baseband processing section of a passive UHF RFID tag for half-duplex communications in the 860-960 MHz range, which implements the EPC(TM) Class-1 Generation-2 (Gen2) protocol. Besides serving identification purposes, the tag also includes a 10-bit, 2kS/s generic signal acquisition interface to allow for signal readouts from the environment (e.g., temperature, pressure, optical or chemical variables). This ability to monitor, record and even react to ambient conditions is expected to promote a new world of applications for RFIDs.
Given the complexity of the protocol and the lack of external batteries, as in the case of active transponders, design efforts has been directed towards minimizing the power consumption of the processor. To this end, different power saving techniques has been considered in the implementation. They include the use of clock gating and power down control strategies or the synthesis of dedicated clocks per processor task. Additionally, most of the blocks of the decoding section of the processor are operated by means of simple trigger pulses at a rate defined by the incoming data (much slower than the master clock signal). The combined effect of these techniques is that every element of the processor always operates at the lowest clock frequency possible and it is only active when strictly required. A sophisticated timing unit able to generate the different clock signals, block operation windows and trigger pulses is the responsible for the application of the aforementioned low-power design techniques.
The processor, which implements all the commands/actions defined by the Gen-2 protocol, has been implemented in a 0.35μm CMOS technology process using automatic tools for both the logic synthesis and layout. It operates from a 1.2V supply voltage and uses a nominal master clock frequency of 1.92 MHz, enough to comply with the Gen2 requirements. Besides, the processor also includes a simple protocol for handling the signal captured from the sensor interface. This protocol takes advantage of commands already defined in the standard, namely, the Write command for reading and storing the captured data into the nonvolatile memory of the tag, and the Read command, for transferring the sensory information to the interrogator. The signal acquisition interface consists of a rail-to-rail input band-limited programmable gain amplifier followed by a capacitive DAC based Successive Approximation Register (SAR) ADC.
The power consumption of the processor has been measured assuming maximum bit-rates for the forward and backward links. During a communication link involving five consecutive commands, the processor consumes less than 2.9μA, assuming worst-case timing conditions. Further, the signal acquisition interface consumes 130nA at 2kS/s and obtains 9.4 bits ENOB (58.4dB SNDR) for a full-scale 300Hz input tone.
VISCUBE: A multi-layer vision chip
A. Zarándy, C. Rekeczky, P. Földesy, R. Carmona-Galán, G. Liñán-Cembrano, S. Gergely, A. Rodríguez-Vázquez and T. Roska
Book Chapter · Focal-Plane Sensor-Processor Chips, pp 181-208, 2011
resumen
doi pdf
Vertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital processor arrays on a four layer structure is introduced. The mixed-signal processor array is designed to perform early image processing, while the role of the digital processor array is to accomplish foveal processing. The architecture supports multiscale, multifovea processing. The chip has been designed on a 0.15um feature sized 3DM2 SOI technology provided by MIT Lincoln Laboratory.
Synthesis and design of nonlinear circuits
A. Rodríguez-Vázquez, M. Delgado-Restituto, J.L. Huertas-Díaz and F. Vidal-Verdú
Book Chapter · Nonlinear and Distributed Circuits, pp 2-1, 2-36, 2005
resumen
doi
Abstract not available
Voltage-to-frequency converters
F. Vidal-Verdú, A. Rodríguez-Vázquez and R.J. Navas-González
Book Chapter · Encyclopedia of RF and Microwave Engineering, Published Online 2005
resumen
doi
Voltage-to-frequency-converters (VFCs) do typically employ relaxation oscillators to generate an output signal whose frequency depends linearly on an input voltage. VFCs are data converters; they are designed to codify the input voltage by means of the output frequency. Hence, they have strong requirements regarding linearity, dynamic range, and stability. On the other hand, compared to other converters, they have the advantage of low cost, particularly for large resolutions; 13 bit resolution is typical, and more than 20 bits are feasible. However, in such a case several milliseconds may be necessary to complete the conversion -the smaller the resolution, the shorter the conversion time.
The serial frequency modulated output provided by VFCs is particularly well suited for telemetry, to send the outcome of a measurement by wire, radio, or fiberoptic links. After the frequency-modulated signal is received, it can be easily codified into a digital word, or converted back into a voltage by a frequency-to-voltage converter. This type of output simplifies galvanic isolation through the use of either an optocoupler or a magnetic coupler. The serial output is also useful for increasing system compactness if throughput requirements are not high. Although many smart monolithic sensors have serial frequency-modulated outputs, a VFC is needed in case we have an output voltage like that of a Wheatstone bridge after being amplified by an instrumentation amplifier, or the output of a generating sensor such as a thermocouple.
This article deals first with the concepts behind voltage to frequency conversion, and then describes the main types of VFCs on the market, their limitations and main applications. Frequency-to-voltage converters are also briefly described.
Mixed analog digital
K. Einwich, J. Hasse, P. Schwarz, C. Grimm, L. Hedrich, T. Ifström, G. Jerke, V. Meyer-Zu-Bexten, A. Rodríguez-Vázquez, R. Romay, I. Rugen-Herzig and M. Thole
Book Chapter · Medea + Design Automation Roadmap, pp 105-121, 2005
resumen
Abstract not available
CMOS mixed-signal flexible vision chips
G. Liñán-Cembrano, L. Carranza-González, S. Espejo-Meana, R. Domínguez-Castro and A. Rodríguez-Vázquez
Book Chapter · Smart Adaptive Systems on Silicon, pp 103-118, 2004
resumen
doi
Today, with 0.18μm technologies fully mature for mixed-signal design, CMOS compatible optical sensors available, and with 0.09μm knocking at the door of designers, we have the pieces to confront the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last years towards the realization of Vision Systems on Chips. Such VSoCs are targeted to integrate in a semiconductor substrate the functions of sensing, image processing in space and time, high-level processing and control of actuators. Based on newest discoveries of neurobiologists about the behavior of mammalian retinas, a new generation of flexible mixed-signal vision chips has been created which feature better Speed vs. Power figures than DSP-based systems. These devices are true mixed-signal microprocessors including standard digital I/O, embedded image and program memories. This chapter presents some concepts related to the architectures, circuits and methodologies associated to the design of these chips. Due to space limitations, and for the sake of illustrating different topics related to the design of such a kind of vision chips we will concentrate on the series of ACE devices developed by our group since 1996, referring the interested reader to some of the references at the end of the chapter.
Vertebrate retina emulation using multi-layer array-processor mixed-signal chips
R. Carmona-Galán, A. Rodríguez-Vázquez, R. Domínguez-Castro and S. Espejo Meana
Book Chapter · Smart Adaptive Systems on Silicon, pp 85-101, 2004
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A bio-inspired model for an analog programmable array processor (APAP), based on stu dies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented here.
PGAs and filters
M. Delgado-Restituto and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 481-521, 2003
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Amplifiers and filters are commonplace devices in the analog front-end (AFE) of communication transmitters-receivers (transceivers, in short). In a general sense, these devices provide the necessary adaptation, in terms of power adjustment and signal isolation, between the transmission media (e.g., atmosphere, free space, cable, twisted-pair, optic fiber) and the digital signal processor (DSP) which performs most of the algorithmic tasks needed to guarantee a reliable transmission/reception of the information. In some cases as, for instance, in wireless transceivers, amplification and filtering may take place at multiple steps along the AFE; often using different technologies (CMOS, silicon bipolar, GaAs) or external passive components (e.g., surface-acoustic wave filters) depending on the frequency range at which operations are realized. In this chapter, following the main stream of the book, we focus on the realization of those amplifiers and filters which are used to drive signals to/from the AFE data converters at the interface with the DSP block, paying special attention on their implementation in inexpensive CMOS technologies. Such amplifiers and filters are symbolically shown in Fig. 14.1, where preceding/following circuits for reception/transmission have been globally called Rx/Tx medium interface, respectively.
High-order cascade multi-bit ΣΔ modulators
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 307-343, 2003
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Motivated by the commercial success of the wireline communication products, mixed-signal designers are being pushed to integrate A/D and D/A interfaces featuring 12- to 16-bit effective resolution for signal bandwidths well in excess of 1MHz. These specifications must be achieved in a low-voltage scenario, making use of poor performance (and often badly characterized) devices, which decreases the 'analog speed' of deep-submicron CMOS processes.
Sigma-delta CMOS ADCs: An overview of the state-of-the-art
A. Rodríguez-Vázquez, F. Medeiro, J.M. de la Rosa, R. del Río, R. Tortosa and B. Pérez-Verdú
Book Chapter · CMOS Telecom Data Converters, pp 37-91, 2003
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As stated in Chapter 1, analog-to-digital conversion involves a number of tasks, namely:
- Sampling the input signal at frequency f s, with prior anti-aliasing filtering and, in some cases, holding the sampled values.
- Quantizing the input sample values with N bits; i.e., mapping each continuous-valued input sample onto the closest discrete-valued level out of the (2ˆN - 1) discrete levels covering the input signal variation interval.
- Encoding the result in a digital representation.
CMOS comparators
R. Domínguez-Castro, M. Delgado-Restituto, A. Rodríguez-Vázquez, J.M. de la Rosa and F. Medeiro
Book Chapter · CMOS Telecom Data Converters, pp 149-182, 2003
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abstract not available
Bandpass sigma-delta A/D converters: Fundamentals, architectures and circuits
J.M. de la Rosa, B. Pérez-Verdú, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
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The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs
Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · Analog Circuit Design: Structured Mixed-Mode Design, Multi-Bit Sigma-Delta Converters, Short Range RF Circuits, pp 235-260, 2002
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This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-um CMOS technology are given and illustrated through experimental results.
Trade-offs in the design of CMOS comparators
A. Rodríguez-Vázquez, M. Delgado-Restituto and J.M. de la Rosa-Utrera
Book Chapter · Trade offs in analog circuit design, pp 407-441, 2002
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This chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 14.2 introduces several comparator architectures and circuits. Then, Section 14.3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the resolution-speed trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 14.4 and new comparator topologies are presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section.
Otras publicaciones
Bandpass Sigma-Delta Modulators: Principles, Architecture and Circuits
A. Rodríguez-Vázquez and J.M. de la Rosa
Course · CMOS Data Converters for Communications. ESD-MSD Mixed Signal Design Cluster, 2002
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Abstract not available
