Encontrados resultados para:
Autor: Eduardo Peralías Macías
Año: Desde 2002
Artículos de revistas
CMOS Front End for Interfacing Spin-Hall Nano-Oscillators for Neuromorphic Computing in the GHz Range
R. Fiorelli, E. Peralias, R. Mendez-Romero, M. Rajabali, A. Kumar, M. Zahedinejad, J. Akerman, F. Moradi, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · Electronics, vol. 12, no. 1, article 230, 2023
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Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4-20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 mu V even for an impedance as large as 300 ohm and a noise figure of 5.3 dB(300 ohm). A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.
Digital Non-Linearity Calibration for ADCs with Redundancy using a new LUT Approach
A. Gines, G. Leger and E. Peralias
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 68, no. 8, pp 3197-3210, 2021
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This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude.
Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs
R. Fiorelli, N. Barabino, F. Silveira and E. Peralias
Journal Paper · Circuits Systems and Signal Processing, vol. 39, pp 2796-2821, 2020
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This paper presents a simple but accurate normalized nonlinear large-signal semiempirical MOS transistor model to be used in monolithic RF Class A-to-C PAs. MOS transistor characteristics, saved in lookup tables, are extracted for different PVT corners, allowing the study of the PA performance spread. Model accuracy is ratified by the excellent matching obtained when comparing data algebraically calculated with electrical simulations of hundreds of PAs, and with the measurement data of a fabricated 2.4 GHz PA.
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda
Journal Paper · International Journal of Circuit Theory and Applications, vol. 47, no. 3, pp 333-349, 2019
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This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs
A.J. Gines, E. Peralias and A. Rueda
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp 2966-2970, 2017
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This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparators produce time-variant offsets depending on the input-signal slope at the sampling instants. These increase residue excursions at the MDAC output, potentially causing overranging and an increment in nonlinear errors. This paper derives close analytical expressions for these effects. The proposed method uses the overranging information to perform a low-cost estimation and correction of the skew error with the following features: 1) very fast convergence (in the order of 1-k input samples); 2) indirect evaluation of the skew error signal, without any previous knowledge of the input signal's frequency distribution; and 3) relatively simple digital logic--basically, two digital comparators and one small accumulator. The method was verified in behavioral and transistor-level simulations. As a demonstrator, its implementation in a 1.8-V 80-dB SNDR 100-Msps SHA-less pipeline ADC in a 0.18-μm CMOS process is shown.
Black-Box Calibration for ADCs with Hard Nonlinear Errors using a Novel INL-Based Additive Code: A Pipeline ADC Case Study
A.J. Ginés, E.J. Peralías and A. Rueda
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 7, pp 1718-1729, 2017
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This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
J. Núñez, A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 89, no. 33, pp 593-609, 2016
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This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 μm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.
Semi-empirical RF MOST model for CMOS 65nm technologies: Theory, extraction method and validation
R. Fiorelli and E. Peralías
Journal Paper · Integration, the VLSI Journal, vol. 52, pp 228-236, 2016
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This paper presents a simple but accurate semi-empirical model especially focused on 65. nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5. GHz and 5.3. GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 203, no. 7, pp 1345-1349, 2015
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This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.
MOST Moderate-Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs
R. Fiorelli, F. Silveira and E. Peralias
Journal Paper · IEEE Transactions on Microwave Theory and Techniques, vol. 62, no. 3, pp. 556-566, 2014
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In this paper, the MOS transistor (MOST) moderate- inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto-optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684μW, an NF of 4.36dB, a power gain of 9.7dB, and a third-order intermodulation intercept point of -4dBm with load and source resistances of 50Ω
Blind adaptive estimation of integral nonlinear errors in ADCs using arbitrary input stimulus
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 60, no. 2, pp 452-461, 2011
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An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.
LC-VCO design optimization methodology based on the g(m)/I(D) ratio for nanometer CMOS technologies
R. Fiorelli, E. Peralias and F. Silveira
Journal Paper · IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 7, pp 1822-1831, 2011
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In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 mu A from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.
On chopper effects in discrete-time ΣΔ modulators
G. Leger, A.J. Ginés-Arteaga, E. Peralías-Macias and A. Rueda
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, no. 9, pp 2438-2449, 2010
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Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.
ADC non-linearity low-cost test through a simplified double-histogram method
M.A. Jalón and E. Peralías
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 26, no. 1, pp 47-58 Sp. Iss., 2010
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This paper introduces a method to reduce the requirements of the test sources for evaluating the non-linearity characteristics of Analogue-to-Digital converters. The method is based on a non-interleaved Double-Histogram test independent of the test signal waveform. It has been validated by simulation results in a 16-bit pipeline A/D converter and by an experimental example using the AD6644 commercial converter.
Enhanced double-histogram test
M.A. Jalón, A. Rueda and E. Peralías
Journal Paper · Electronics Letters, vol. 45, no. 7, pp 349-350, 2009
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A method is introduced for reducing experimental setup complexity and time costs associated with the A/D converters linearity test using double histograms. The method is independent of the waveform of the test signal and it does not require inclusion of any time-interleaved technique to reduce time-drift effects.
Simple evaluation of the nonlinearity signature of an ADC using a spectral approach
E.J. Peralías, M.A. Jalón and A. Rueda
Journal Paper · VLSI Design, vol. 2008, article 657207, 2008
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This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values. Copyright © 2008 E. J. Peralías et al.
New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 57, no. 1-2, pp 57-68, 2008
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A novel swapping technique for stage non-linear error calibration in Pipeline ADCs (analogue-to-digital converters) is presented in this paper. The proposed algorithm obtains an estimation of the mismatch between sampling capacitors in the MDAC (multiplying digital-to-analogue converter) inside each stage, without the necessity of interrupting the ADC operation, and therefore, suitable for background calibration applications. The technique also shows its applicability for the amplifier finite DC-gain error, providing a low-cost solution for full calibration of the main static errors in the Pipeline topology with less convergence time, memory resources and simpler calibration hardware than other existing calibration methods. In addition, this work overcomes practical limitations of previous adaptive approaches based on capacitor swapping by introducing a novel modulation scheme. This new scheme minimizes the impact on the analogue part and employs a very simple digital modulation logic.
A CMOS optical PSD with submicrometer resolution
R. Doldán, E. Peralías, A. Yufera and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 53, no. 2-3, pp 109-118, 2007
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This paper presents the design of an optical Position Sensing Detector (PSD) for application in biological material gene identification. The system is able to measure changes in the position of a light spot emitted by a Vertical Cavity Surface Emitting Laser (VCSEL). Changes in spot position are produced by the deflections of a microcantilever used to sense the hybridisation process of the biological material. Detection of these deflections requires submicrometer resolution. The photodetectors and the detection algorithm proposed in this paper have been designed and optimized for this resolution. A 0.35 mu m CMOS prototype consisting of an array of 22 PSDs has been implemented and experimentally characterized. The obtained results confirm that displacements of the light spot position as low as 0.15 mu m can be detected.
A highly sensitive microsystem based on nanomechanical biosensors for genomics applications
L.M. Lechuga,J. Tamayo, M. Álvarez, L.G. Carrascosa, A. Yufera, R. Doldán, E. Peralías, A. Rueda, J.A. Plaza, K. Zinoviev, C. Domínguez, A. Zaballos, M. Moreno, C. Martínez-A, D. Wenn, N. Harris, C. Bringer, V. Bardinal, T. Camps, C. Vergnenègre, C. Fontaine, V. Díaz and A. Bernad
Journal Paper · Sensors and Actuators, B: Chemical, vol. 118, no. 1-2, pp 2-10, 2006
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Microcantilever-based biosensors are a promising tool to detect biomolecular interactions in a direct way with high accuracy. We show the development of a portable biosensor microsystem able to detect nucleic acid hybridization with high sensitivity. The microsystem comprises an array of 20 micromechanical cantilevers produced in silicon technology, a polymer microfluidic system for delivery of the samples, an array of 20 vertical cavity surface emitting lasers (VCSELs) with collimated beams thanks to an integrated microlens array, an optical coupling element to provide the optical path required, and chips with the photodetectors and the CMOS circuitry for signal acquisition and conditioning, capable of measuring the cantilever deflection with sub-nanometer resolution. Robust immobilization and regeneration procedures have been implemented for the oligonucleotide receptor sequences. In a further innovation, an optical waveguide cantilever transducer has been also developed in order to improve the final performance of the device. This has a number of advantages in terms of a simple optical geometry and improved sensitivity.
Selective Clock-Gating for Low-Power Synchronous Counters
P. Parra, A.J. Acosta, R. Jiménez and M. Valencia
Journal Paper · Journal of Low Power Electronics, vol. 1, no. 1, pp 11-19, 2005
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With current technologies and applications, dynamic power reduction is of great technological interest. The objective of this paper is to explore the applicability of clock gating techniques to counters in order to reduce the power consumption as well as to compare different power figures in counting structures. Counters are widely used in current VLSI digital circuits, and optimized low-power versions of them are of important concern. Different ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits with different synchronization schemes. The correct selection of bits where clock gating is applied and the suitable composition of groups of bits are essential but are not straightforward when applying this technique. We have found that some specific groupings of bits are the best options when applying clock gating to reduce power consumption.
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs
G. Léger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Transactions on Circuits and Systems I, vol. 51, no. 1, pp 140-150, 2004
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Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions. © 2004 IEEE.
Oscillation-based test in oversampled ΣΔ modulators modulators
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · Microelectronics Journal, vol. 33, no. 10, pp 799-806, 2002
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This paper discusses a way of applying the oscillation-based test (OBT)/oscillation-based built-in-self test concept to oversampled ΣΔ modulators, exploiting previous experience coined through the implementation of OBT in SC integrated filters. Analytical and simulation results demonstrate that it is always feasible to find out an OBT configuration for a typical discrete-time second-order modulator structure without adding a substantial extra circuitry, but only resorting to local feedback loops. A feedback strategy can be chosen providing enough freedom to force oscillations, which can be worthwhile for testing purposes. The selected oscillation parameters allow us to establish criteria for a high fault coverage.
On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits
D. Vázquez, G. Huertas, G. Leger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 201-211, 2002
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This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.
Practical oscillation-based test of integrated filters
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Design & Test of Computers, vol. 19, no. 6, pp 64-72, 2002
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Oscillation-based test techniques show promise in detecting faults in mixed-signal circuits and require little modification to the circuit under test. Comparing both the oscillation's amplitude and frequency yields acceptable test quality.
Testing mixed-signal cores: A practical oscillation-based test in an analog macrocell
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Design & Test of Computers, vol. 19, no. 6, pp 73-82, 2002
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A formal set of design decisions can aid in using oscillation-based test for analog subsystems in SoCs. The goal is to offer designers testing options that don't have significant area overhead, performance degradation, or test time.
VHDL behavioural modelling of pipeline analog to digital converters
A.J. Acosta, E. Peralias, A. Rueda and J.L. Huertas
Journal Paper · Measurement, vol. 31, no. 1, pp 47-60, 2002
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This paper describes a VHDL implementation of a behavioural model for pipeline analog to digital converters (ADCs). The goal is using this VHDL description to facilitate the synthesis of the digital part, which in our example includes digital correction, digital calibration, and control of the ADC testing modes. Among other aspects of general interest, we will show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. As an application example, an ADC of 10-bits and 10 MSamples/s has been modelled and simulated. Results front these high level simulations carried out using QuickHDL in Mentor Graphics are compared with those obtained experimentally from a silicon prototype, validating the suitability of the model. (C) 2002 Elsevier Science Ltd. All rights reserved.
Congresos
Integration of two High-Performance Mixed-Signal Data Conversion IPs
G. Leger, A. Gines, E. Peralias, J.M. Mora and A. Ragel
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2021
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This brief presents the experience of integrating two high-performance Data Converter IPs, an ADC and a DAC, in a single rad-hard test-chip. A system-level perspective is taken, underlining the importance of Design-for-Testability (DfT) structures and tuning structures for debugging purposes and achieving first-time right silicon. Modeling the interactions between domains (PCB, package, analog and digital) is also highlighted as a key to success, particularly for high performance circuits operating at the limits of technology.
Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions based on the Matrix Exponential
J.A. Serrano, A.J. Gines and E. Peralías
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponential. The method is fully general and suitable for different circuits, including switched-capacitor (SC) architectures, analog to digital converters (Pipeline, SAR, Sigma-Delta ADCs) or digital to analog converters. For illustration purpose in this paper, an analog signal processing front-end for discrete-time data acquisition system is considered as case study. The circuit comprises a Flip-Around Sample&Hold followed by a Programmable Gain Amplifier (PGA), based on a Correlated Double-Sampling amplifier, and a back-end ADC. The model includes non-linearity associated to switches, capacitive parasitics, finite nonlinear DC-gain and non-linear settling behavior including slew-rate. Comparison with traditional ODE numerical solvers shows a reduction of the computation time in almost two orders of magnitude with negligible difference in terms of accuracy.
Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy
A. Lopez-Angulo, A. Gines and E. Peralias
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the least-significant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy
A. Lopez-Angulo, A. Gines and E. Peralias
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2020
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This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration with negligible impact on the analog section. It reuses some of the capacitors in the array to also com-pensate the comparison offset, preventing redundancy interval saturation during the error measurement phase. The effec-tiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit split-CDAC SAR ADC case study.
Non-linear calibration of pipeline ADCs using a histogram-based estimation of the redundant INL
A. Gines, G. Leger and E. Peralias
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2020
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This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT-based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.
Mismatch and Offset Calibration in Redundant SAR ADC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
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This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the leastsignificant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.
Fast Simulation of Non-linear Circuits using Semi-Analytical Solutions based on the Matrix Exponential
J.A. Serrano, A.J. Ginés, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
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This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponential. The method is fully general and suitable for different circuits, including switched-capacitor (SC) architectures, analog to digital converters (Pipeline, SAR, Sigma-Delta ADCs) or digital to analog converters (SC, Current-steering DACs). For illustration purpose in this paper, an analog signal processing front-end for discrete-time data acquisition system is considered as case study. The circuit comprises a Flip-Around Sample&Hold followed by a programmable gain amplifier (PGA) based on a Correlated Double-Sampling amplifier. The model includes non-linearity associated to switches, capacitive parasitics, finite non-linear Dcgain and non-linear settling behavior including slew-rate. Comparison with traditional ODE numerical solvers shows a reduction of the computation time in more than two orders of magnitude with negligible difference in terms of accuracy.
SAR ADCs with Redundant Split-capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
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This paper analyzes the effect of redundancy in Successive Approximation Register (SAR) ADCs with splitcapacitor DAC (Split-CDAC). It also presents a general hardware-based model which provides closed-relationships, suitable for design, between the capacitor scale factors, the bridge capacitance and the practical implementation of the digital correction logic. In conventional binary Split-CDAC (without redundancy), the voltage at the floating nets in the array could exceed the ADC references, stressing the operation of switches. Using the proposed model, we will show that this effect also occurs in SAR ADCs with redundancy, but with some particularities depending on the selection of the weighting coefficients in the digital correction logic. We will demonstrate the excursion can be controlled, as in the binary case, with a simple DAC modification which includes an extra limiting capacitor.
Redundant SAR ADCs with Split-Capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2018
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This paper presents an unified formulation for Successive Approximation Register (SAR) ADCs with splitcapacitor arrays providing explicit expressions, suitable for design, of the relationships between capacitors and the weighting coefficient in the digital correction logic. A closed-form estimation of the optimum limiting capacitor to control the voltage excursion in the floating node of the Least Significant Bit (LSB) array is, in the authors´ bibliography best knowledge, firstly derived in this work. The proposed hardware-based formulation has been verified by behavioral and electrical simulations.
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach
A. Gines, A. Lopez-Angulo, E. Peralias and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
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This paper analyzes the state-of-the-art in Successive-Approximation-Register (SAR) ADCs with digital redundancy using a unified nomenclature and modeling. Redundancy provides tolerance intervals for dealing with comparison errors during the SAR search algorithm due to incomplete settling in the DAC. Employing redundancy improves conversion speed/power trade-off as well as relaxes switch sizes and comparator design. The proposed description presents a common theoretical and physical framework for analyzing existing (apparently different) techniques in the bibliography, independently of the practical realization (binary or arbitrary scaled capacitors with redundant bits) and switching schemes. Several examples are modeled and simulated using the proposed approach.
Unified Hardware-Based Description for SAR ADCs with Redundancy
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
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This paper presents an analysis and review of digital redundancy techniques in Successive-Approximation-Register (SAR) ADCs for correction of comparator errors during the SAR search algorithm. The use of redundancy provides safety margin for dealing with incomplete settling in the DAC network, improving conversion speed and power, as well as relaxing switch sizes and comparator design. Techniques like binaryscaled, radix-based or arbitrary weighing capacitors with redundant bits are discussed using a unified nomenclature and modeling. The proposed unified description is closely related to the hardware realization eliminating the gap between theoretical and physical implementations, and allowing a clear identification of pros and cons of different approaches. For illustration purpose, several examples are modeled and simulated using the proposed description.
On the limits of machine learning-based test: A calibrated mixed-signal system case study
M.J. Barragan, G. Leger, A. Gines, E. Peralias and A. Rueda
Conference · Design, Automation and Test in Europe DATE 2017
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Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system -i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.
Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference · International Mixed-Signals Testing Workshop IMSTW 2016
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This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed highperformance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in the order of 12 bits and 80 Msps of sampling frequency.
Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference · IEEE European Test Symposium ETS 2016
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This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutionsin the order of 13 bits and 100Msps of sampling frequency.
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J. Núñez, A.J. Gines, E. Peralías and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
resumen
High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18μm commercial CMOS process.
Power Optimization and Stage Op-amp Linearity Relaxation in Pipeline ADCs with Digital Comparator Offset Calibration
A. Ginés, E. Peralias, C. Aledo and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014
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This paper presents a power optimization technique for Pipeline ADCs using digital background calibration of comparator offsets as an extra design variable. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax the power consumption of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. The proposal was validated using realistic hardware-behavioral models and transistor-level simulations. A 1.8V 15-bit 74dB-SNDR 100Msps Pipeline ADC was used as a demonstrator. Thanks to comparator calibration, the total power of stage subADCs was reduced by 75%, while a factor of 19% was found in stage amplifiers.
INL Systematic Reduced Test Technique for Pipeline ADCs
E. Peralías, A. Ginés and A. Rueda
Conference · IEEE European Test Symposium ETS 2014
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This paper presents a procedure to implement a high efficient test of the Integral Non-linearity (INL) of Pipeline ADCs using an extremely reduced set of test input amplitude levels (one order of magnitude lower than the total number of codes in the ADC). For a given architecture, the method provides the way to determine these levels to robustly capture the nonlinearity information. The location of each test level within the input range has low sensitivity to the internal ADC noise, and therefore, they are a good basis to continuously monitor the impact of process, aging and environment conditions variations (PVT) on the non-linearity, as well as miscalibration and possible failures in both foreground and background applications. The proposed method has been validated by realistic behavioral models in several examples.
Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
A.J. Ginés, G. Leger, E. Peralías and A. Rueda
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2014
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This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.
Mixed-Signal Techniques for Robust Auto-Tuning of Split-Tuned PLL Frequency Synthesizers
C. Aledo, A.J. Ginés, E. Peralías and A. Rueda
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
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This paper proposes two different phase-locked loop (PLL) auto-tuning techniques for low-cost sub-band selec-tion in split-tuned frequency synthesizers. The methods conti-nuously monitor the tuning voltage Vtune of the voltage-controlled oscillator (VCO) using two comparators whose threshold voltages define the PLL design region. Considering the comparators deci-sion, a simple digital control unit (DCU) generates a correction signal which assures Vtune is always within the allowable range, hence concurrently dealing with process, voltage and tempera-ture (PVT) variations. Two alternative algorithms depending on the DCU implementation have been proposed as trade-off between hardware complexity and convergence response. Both algorithms have been experimentally validated in a 1.2V PLL frequency synthesizer. This PLL block is part of a monolithical 2.4GHz IEEE 802.15.4 ZigBee transceiver implemented in a RF 90nm CMOS technology.
Background Calibration of Comparator Offsets in Pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · International Conference on Analog VLSI Circuits AVIC 2012
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A digital low-cost adaptive technique for calibrating comparator offsets in Pipeline ADCs is proposed in this paper. The method is suitable for a generic topology including standalone dynamic-latch comparators (SA-DLCs) with no external reference and no preamplifier. It performs an accurate blind estimation and an adaptive correction of comparator offsets without redundant hardware or calibration stimuli, and without interruption of the ADC operation (background mode). The method also allows relaxing the power consumption of stage amplifiers, since their output swing and driving capability are significantly reduced. The technique has been validated by realistic hardware-behavioral models and transistor-level simulations.
Semi-empirical model of MOST and passive devices focused on narrowband RF blocks
R. Fiorelli, F. Silveira, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2012
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This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions of MOST and the data is extracted as function of the gm=ID characteristic; for the passive devices the LUTs include a simplified model of the element and its principal parasitic at the working frequency f0. These semi-empirical models are validated by designing a set of 2.4-GHz LNAs and 2.4-GHz and 5-GHz VCOs in three different MOST inversion regions.
Self-Biased Input Common-Mode Generation for Improving Dynamic Range and Yield in Inverter-Based Filters
A.J. Ginés, A. Villegas, A. Rueda and E. Peralías
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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A simple and robust circuit for the input commonmode voltage generation in CMOS pseudo-differential inverter-based transconductors is proposed. The solution can improve the in-band IIP3 in 7.8dBVp and the 1-dB compression point in 5.3dBVp compared to conventional approaches, with less noise, power consumption and occupied die area. A 1.2V 3.42mW 1.3-3.7MHz high-linear 8th order bandpass complex filter is presented as demonstrator in a CMOS 90nm process. The yield for an image rejection ration IRR above 50dB is 86%, which represents a 31% improvement respect to the classical approach.
An all-inversion-region MOST design methodology applied to a ratioless differential LC-VCO
R. Fiorelli, F. Silveira and E. Peralías
Conference · Conference on Ph.D. Research in Microelectronics and Electronics PRIME 2012
resumen
This paper presents a general optimization method- ology for analog blocks in RF applications, with CMOS nanome- ter technologies, based on the complete exploration of all-in- version regions of MOS transistor (MOST). The fundamental tool is the systematic use of the MOST gm/ID technique and the description of the real behavior of all devices by means of semi-empirical models. To exemplify this technique, the differen- tial ratioless cross-coupled LC-tank voltage controlled oscillator (LC-VCO) circuit is studied. The implemented design flow minimizes the LC-VCO phase noise considering the constraints of current consumption, output common-mode voltage and output amplitude. To verify the method, six LC-VCO were designed and validated by comparing them with the corresponding electrical simulations.
Analysis of steady-state common-mode response in differential LC-VCOs
R. Doldán, A.J. Ginés, E. Peralías and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
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This paper analyzes the common-mode response of LC voltage-controlled oscillators (VCOs) in DC and periodic steady state regimes. The dependence of the common-mode voltage (v cm) on the oscillation amplitude is theoretically studied. Closed and simple expressions for v cm suitable for the VCO design and optimization are derived. The agreement with transistor level simulations has been verified in a 1.2V low-power 90nm CMOS case of study.
A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard
A. Villegas, D. Vázquez, E. Peralías and A. Rueda
Conference · European Solid-State Circuits Conference ESSCIRC 2011
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This paper presents a fully differential 1.2V 8th-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SFDR, noise and selectivity, demonstrated by experimental measurements from a fabricated prototype. © 2011 IEEE.
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS
R. Fiorelli, A. Villegas, E. Peralías, D. Vázquez and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area and power consumption. Also, moderate and weak inversions regions were selected for the operation of the principal transistors. The front-end prototype has been implemented in a 90 nm RF process and occupies a chip area of 0.74 mm2 including on-chip inductors. Very competitive results are observed: a maximum conversion gain (CG) of 30 dB, a DSB noise figure of 7.5 dB, a maximum IIP3 of -12.8 dBm and IIP2 of 14.4 dBm while it consumes 4.7 mW from a 1.2 V supply. © 2011 IEEE.
Power Optimization of CMOS Programmable Gain Amplifiers with High Dynamic Range and Common-Mode Feed-Forward Circuit
A.J. Gines, R. Doldán, A. Rueda and E. Peralias
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2010
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A 1.2V 1.95mW low-power Programmable Gain Amplifier (PGA) with high-input range is proposed and implemented in a 90nm CMOS process. The PGA is formed by three stages with a bandwidth of 20MHz for a 2pF capacitive load. Gain is in the range between 0 and 72dB in steps of 6dB. The stage core consists in a differential super-source follower (SSF) with programmable resistive degeneration. Each stage uses a front-end capacitive decoupling network which allows a robust selection of the operating point for improving linearity and reducing power. Further power saving is achieved with a common-mode feed-forward circuit (CMFFC), based on a simple current conveyor. The total PGA area is 165×33μm2 in a 90nm CMOS process. Post-layout simulations at maximum gain show a THD of -57dB and -42dB for output amplitudes of 0.6Vpp and 1.2Vpp, respectively. Input referred noise is just 10.2nVrms/√Hz from 1MHz to 4MHz.
A low-power programmable gain amplifier with optimized input range in 90nm CMOS process
A.J. Ginés, R. Doldán, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Abstract not available
A 5 GHz LC-VCO with active common mode feedback circuit in sub-micrometer cmos technology
R. Doldán-Lorenzo, A.J. Ginés-Arteaga, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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A 1.2V 5GHz low-cost voltage-controlled oscillator (VCO) with active common mode feedback has been implemented in a CMOS/RF 90nm technology for a robust I/Q generation using a frequency divider-by-2 (DIV2). As the input common mode of the DIV2 affects critically its performance, a calibration method to correct the output common mode of the VCO has been proposed and validated through post-layout simulations.
A fully differential monolithic 2.4 GHz PA for IEEE 802.15.4 based on efficiency design flow
R. Fiorelli, E. Peralías, N. Barabino and F. Silveira
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2010
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This work presents the design and implementation of a differential class C power amplifier (PA) in a 90nm CMOS technology, specified to be used in a IEEE802.15.4 low power transceiver. The design is based on a PA efficiency design flow implemented in MATLAB which enables to reach very good power efficiency figures. The method is validated comparing MATLAB predicted data and post-layout SpectreRF simulated results. Post-layout simulations show a Power Amplifier Efficiency (PAE) of 46.5%, a power gain Gpow of 26dB, and an output power Pout of 1.9dBm for a 100 Ohm load, working with a supply voltage VDD = 0.65V and a MOS DC current ID of 4.6mA. The total area is 700um x 710um. ©2010 IEEE.
An adaptive BIST for INL estimation of ADCs without histogram evaluation
A.J. Ginés, E. Peralías and A. Rueda
Conference · IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop IMS3TW 2010
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A robust low-cost test solution for static characterization of analog-to-digital converters (ADCs) is presented in this paper. It uses an adaptive algorithm to perform a blind and accurate estimation of the Integral Non-Linearity (INL) of the ADC under test (ADCUT). Its main applications are for: a) simple off-line ADC test using modern mixed-signal ATEs (Automatic Test Equipments) without requiring any dedicated input stimulus, b) Built-in Self-test (BIST) for ADC INL evaluation either in concurrent (on-line) or non-concurrent (off-line) modes. The test validation has been performed through realistic behavioral simulations including noise, mismatch and non-linear errors. Experimental results for a custom-designed 10-bit Successive Approximation (SAR) ADC are also reported. ©2010 IEEE.
On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation
A.J. Ginés, R. Doldán, M.J. Barragán, A. Rueda and E. Peralías
Conference · International Symposium on Circuits and Systems ISCAS 2010
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In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude between 0 degrees C and 100 degrees C with negligible impact on the phase noise. Worst case estimations of the VCO phase noise after layout parasitic extraction are -110.1dBc/Hz and -126.6dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. Its nominal current consumption is 198μA (plus 22.5μA for biasing) and it occupies 370x530μm2.
Random Chopping in Sigma-Delta Modulators
G. Léger, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2009
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ΣΔ modulators make a clever use of oversampling
and exhibit inherent monotonicity, high linearity and large
dynamic range but a restricted frequency range. As a result
ΣΔ modulators are often the preferred option for sensor and
instrumentation. Offset and Flicker noise are usual concerns
for this type of applications and one way to minimize their
effects is to use a chopper in the front-end integrator of the
modulator. Frequency-shaped random chopping has been proposed
to minimize the impact of reference voltage interference.
It is shown in this paper that the chopper signal is not the
only term that modulates the offset and Flicker noise and that
unwanted crosstalk can significantly degrade the performance of
the modulator.
Phase noise-consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies
R. Fiorelli, F. Silveira and E. Peralías
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2009
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An LC-VCO design optimization, based on the gm/ID methodology, is presented throughout this work, highlighting how, by applying all regions of inversion of the MOS transistor, the trade-o! between phase noise and current consumption can be optimized for the application. Both transistor compact model equations and transistor data acquired from simulation are used to obtain gm/ID curves as well as normalized capacitances. Influence of tank elements' characteristics in the VCO performance is also discussed. Results of applying the methodology in the design of two VCOs in 0.35um and 90nm CMOS processes are described. Measurement results for the 915MHz VCO designed in 0.35um CMOS technology are also presented, obtaining a current consumption of 3mA with a phase noise (L) of -107dBc/Hz @1MHz. The 2.4GHz VCO designed in a 90nm radiofrequency technology shows a current consumption of 400uA with a L of -111.4dBc/Hz @600kHz. Copyright 2009 ACM.
ADC non-linearity low-cost test through a simplified double-histogram method
M.A. Jalón and E. Peralías
Conference · IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop IMS3TW 2009
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This paper introduces a method to reduce the requirements of the test sources for evaluating the nonlinearity characteristics of Analogue-to-Digital converters. The method is based on a non-interleaved Double-Histogram test independent of the test signal waveform. It has been validated by simulation results in a 16-bit pipeline A/D converter and by an experimental example using the AD6644 commercial converter. ©2009 IEEE.
On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation
A.J. Ginés, E. Peralías and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2009
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An adaptive digital built-in self-test (BIST) for the static characterisation of analogue-to-digital converters (ADCs) has been developed in this work. The proposed technique performs a blind and accurate estimation of the Integral Non-Linearity (INL) of the ADC under test (ADCUT) without affecting to the normal converter operation, using any test stimuli or replicated hardware. The practical implementation of the BIST technique implies no modifications on the analogue section of the ADCUT and uses a very simple low-cost digital logic, which overcomes the classical area overhead of histogram-based approaches for INL measurement.
A survey on digital background calibration of ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2009
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In this paper, a general description of digital ADC calibration approaches in current state-of-the-art is presented, with particular emphasis in Pipeline converters. The study performs a classification of the existing techniques considering two basic aspects: a) the principle of operation and the particular errors which can be compensated after calibration, b) the process from which a measurement of the errors, and therefore the calibrated output code, is obtained. Attention will be paid to those approaches applied in background mode and hence not requiring the interruption of the normal ADC operation.
A 2.5MHz bandpass active complex filter with 2.4MHz bandwidth for wireless communications
A. Villegas, R. Bianca, A. Ginés, R. Doldán, M.A. Jalón, A.J. Acosta, E. Peralías, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2008
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This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V).
A 2.4 GHz LNA in a 90-nm CMOS technology designed with ACM model
R. Fiorelli, F. Silveira, E. Peralías, D. Vazquez, A. Rueda and J.L Huertas
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2008
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As part of a Low-IF ZigBee receiver, a 2.4GHz differential common source low noise amplifier, implemented in a 90nm mixed/RF 7M CMOS process and designed in moderate inversion, is presented in this work. Design methodology and simulation results from Spectre-RF simulator are presented. With 2.5V supply voltage, the LNA achieves a noise figure of 2.5dB, an IIP3 of 1dB and gain higher than 10dB, with a current consumption of 12mA. The LNA area without pads is 720m x 710m. Copyright 2008 ACM.
A 5 GHz wide tuning range LC-VCO in sub-micrometer CMOS technology
R.D. Lorenzo, A.J. Ginés-Arteaga, A. Rueda and E. Peralías
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
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A 1.2V low-cost voltage-controlled oscillator (VCO) has been implemented in a CMOS/RF 90nm technology. The VCO, which uses a LC- tank topology, has a centre frequency of 5GHz with a 30% tuning range from 4.24GHz to 5.74GHz. Worst case estimations of the phase noise after layout and package parasitic extraction are -98.8dBc/Hz and -115dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. The power consumption is 2.52mW and it occupies less than 0.07mm(2).
A 1.2V 5.14 mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4 GHz ZigBee applications
A.J. Ginés, R. Doldán, A. Villegas, A.J. Acosta, M.A Jalón, D. Vázquez, A. Rueda and E. Peralías
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
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A low-cost 1.2V 5.14mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90nm CNIOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of-105.9dBc/Hz at 1MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209x422 mu m(2).
Novel swapping techniques for background calibration of capacitor mismatching in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · Symposium on Integrated Circuits and System Design SBCCI 2007
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A novel swapping technique for calibration of the stage non-linear errors in Pipeline ADCs is proposed in this paper. The algorithm obtains an estimation of the mismatching between sampling capacitors in practical SC implementations of the multiplying-DAC without the necessity of interrupting the converter operation, and therefore, suitable for both foreground and background calibration applications. This work overcomes the practical limitations of previous adaptive approaches based on the capacitor swapping introducing a novel modulation scheme which minimizes the impact on the analogue part and employs a simple calibration logic.
Improved background algorithms for pipeline ADC full calibration
A.J. Ginés, E. Peralías and A. Rueda
Conference · International Symposium on Circuits and Systems ISCAS 2007
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A unified description of the correlation-based techniques for background calibration of Pipeline ADCs using additive modulation at the MDAC output is presented in this paper. Two different algorithms for full calibration of this kind of converter which at least a factor 2 improvement in convergence speed, memory resources and stage output swing requirements over previous MDAC modulation approaches are also proposed.
Digital auto-tuning system for analog filters
G. Zatorre, S. Celma, C. Aldea, N. Medrano and E. Peralías
Conference · International Caribbean Conference on Devices, Circuits and Systems ICCDCS 2006
resumen
In this paper, a new self-tuning digital technique is reported for analog filters over VHP (very high frequency) applications, based on phase detector. By using a 0.35 um Mixed Signal CMOS process, changes in frequency response of a 3rd-order low pass filter can be tuned with a 3% error over the designed value. This technique confirms the feasibility of the proposed scheme in analog filter applications. The system consumes less area, power and tuning time than other proposed schemes. Simulation results show the building viability in a 10 MHz low pass filter. © 2006 IEEE.
Tuning system for CMOS HF analog filters
G. Zatorre, S. Celma, C. Aldea, N. Medrano and E. Peralías
Conference · IEEE Mediterranean Electrotechnical Conference MELECON 2006
resumen
A profound study of a new digital AT (Auto-Tuning) technique for analog filters over very HF (High Frequency) applications is reported in this paper. A 3% precision matching a 3rd-order LPF (Low Pass Filter) characteristic frequency is shown using a 0.35 um CMOS technology. The system consumes less area, power and tuning time than other proposed schemes. Post-layout simulation results show the building viability in a 10 MHz LPF. © 2006 IEEE.
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs(1)
A.J. Ginés, E. Peralías and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
resumen
This paper presents a theoretical analysis of the statistical requirements of a background correlation-based technique for calibration of Pipeline ADCs. The calibration algorithm estimates adaptively the appropriate additive error codes which compensate both the gain and non-linear errors in the stage under calibration (SUC). Close equations for the transient evolution towards the stationary situation are obtained. Expressions for the effective number of bits (ENOB) and signal-to-noise ratio (SNR) at any updating step are also derived.
Digital self-tuning technique for continuous-time filters
G. Zatorre-Navarro, E. Peralías, S. Celma-Pueyo, C. Aldea-Chagoyen and N.M. Marqués
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2005
resumen
pdf
In this paper, a new auto-tuning digital technique is reported for continuous-time filters over VHF (very high frequency) applications, based on phase detector. By using a 0.35 um Mixed Signal CMOS process, changes in frequency response of a 3rd-order low pass filter can be tuned with a 3% error over the designed value. This technique confirms the feasibility of the proposed scheme in continuous-time filter applications. The system consumes less area, power and tuning time than other proposed schemes. Simulated results show the building viability in a 10 MHz low pass filter.
Mixed-mode simulation of optical-based systems: PSD application
R. Doldán, E. Peralías, A. Yufera and A. Rueda
Conference · Conference on Bioengineered and Bioinspired Systems II, 2005
resumen
This paper reports a new model for electrical simulation of photodetector cells, that includes its complete dynamics, and enables full system characterization, both optical and electrical parts by using the same simulation environment (Spectre in our case). The modelling of the optical parts presented in this work allows the designer to change parameters such as incident spot position and optical power, speed in spot position, photodevices responsivity, pixel fill-factor, etc. The paper presents the design and the simulation-based verification of a Position Sensing Detection (PSD) system for applications with resolutions in the micrometer range and with spot movement tracking operation originated in a DNA sensing process.
Full calibration digital techniques for pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · International Symposium on Circuits and Systems ISCAS 2005
resumen
This paper presents a new digital algorithm for full calibration of Pipeline ADCs with digital redundancy. The proposed algorithm corrects both the MDAC gain error of the stage under calibration (SUC) and its non-linear errors. It is based on the modulation of the analogue output of the SUC using a digital control signal to introduce a constant displacement in the references of the comparators in the SUC sub-ADC without reduction of the input dynamic rate. This process can be performed without interruption of the conversion (background mode) including a digital pseudo-random number generator (RNG). The foreground implementation of this algorithm uses a DC calibration stimulus which relaxes the hardware requirements.
Noisy signal based background technique for gain error correction in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen
The paper presents a new digital technique for background calibration of gain errors in pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration (SUC) and the global gain error associated with the least significant stages. This process is performed without interruption of the conversion and without reduction of the dynamic range. It uses a stage with two input-output characteristics depending on the value of a digital pseudorandom noisy signal to modulate the output residue of the SUC and to estimate the calibration code by an adaptive averaging process. The proposed method introduces no significant modifications in the analogue blocks of the pipeline ADCs, making this technique a very promising alternative for background calibration of the nonlinearity associated with the gain errors. Simulation results have proved the stability of the algorithm and the tracking capability for fast gain error changes considering second order effects in both the sub-ADC of the SUC and the back-end stages.
Digital background gain error correction in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen
This paper presents a new digital technique for background calibration of gain errors in Pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.
Digital background calibration technique for pipeline ADCs with multi-bit stages
A.J. Ginés, E. Peralías and A. Rueda
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2003
resumen
This paper presents a technique for background calibration of Pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations Of the LMS algorithm have been studied, concluding that the traditional SS-LMS algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering a SD-LMS implementation.
A mixed-signal design reuse methodology based on parametric behavioural models with non-ideal effects
A.J. Ginés, E. Peralías, A. Rueda, N.M. Madrid and R. Seepold
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen
Current System-on-Chip (SoC) designs incorporate an increasing number of mixed-signal components. Design reuse techniques have proved successful for digital design but these rules are difficult to transfer to mixed-signal design. A top-down methodology is missing but the low level of abstraction in designs makes system integration and verification a very difficult, tedious and complex task. This paper presents a contribution to mixed-signal design reuse where a design methodology is proposed based on modular and parametric behavioural components. They support a design process where non-ideal effects can be incorporated in an incremental way, allowing easy architectural selection and accurate simulations. A working example is used through the paper to highlight and validate the applicability of the methodology.
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Capítulos de libros
Design of an energy efficient ZigBee transceiver
A. Ginés, R. Fiorelli, A. Villegas, R. Doldán, M. Barragán, D. Vázquez, A. Rueda and E. Peralías
Book Chapter · Mixed-Signal Circuits, pp 171-203, 2018
resumen
doi
This chapter tries to summarize our experience in the development of the analog front-end part of 2.4 GHz ZigBee transceivers with the main objective of optimizing power consumption during normal operation in both reception and transmission modes. Other interesting design aspects, such as optimizing the transceiver protocol, the design of the digital subsystems, or managing the sleep modes, have not been included due to space limitation. To gather together the presented design ideas, the chapter concludes in Section 7.5 with an example of a complementary metal-oxide semiconductor (CMOS) integrated transceiver analog front-end. The competitive experimental performances for this integration endorse the employed design flow, procedures, and analysis.
An all-inversion-region gm/ID based design methodology for radiofrequency blocks in CMOS nanometer technologies
R. Fiorelli, E. Peralías and F. Silveira
Book Chapter · Wireless Radio-Frequency Standards and System Design: Advanced Techniques, pp 15-39, 2012
resumen
doi pdf
This chapter presents a design optimization methodology for analog radiofrequency (RF) blocks based on the gm/ID technique and on the exploration of all-inversion regions (from weak inversion or sub-threshold to strong inversion or above threshold) of the MOS transistor in nanometer technologies. The use of semi-empirical models of MOS transistors and passive components, as inductors or capacitors, assures accurate designs, reducing time and efforts for transferring the initial block specifications to a compliant design. This methodology permits the generation of graphical maps to visualize the evolution of the circuit characteristics when sweeping both the inversion zone and the bias current, allowing reaching very good compromises between performance aspects of the circuit (e.g. noise and power consumption) for a set of initial specifications. In order to demonstrate the effectiveness of this methodology, it is applied in the design of two basic blocks of RF transceivers: low noise amplifiers (LNAs) and voltage controlled oscillators (VCOs), implemented in two different nanometer technologies and specified to be part of a 2.4 GHz transceiver. A possible design flow of each block is provided; resulting designs are implemented and verified both with simulations and measurements.
Behavioral modeling of multistage ADCs and its use for design, calibration and test
E. Peralías and A. Rueda
Book Chapter · Test and Design-for-Testability in Mixed-Signal Integrated Circuits, pp 163-214, 2004
resumen
doi
This chapter provides a general model for the static behavior description of multistage ADCs that intends to be independent of the topologies and design techniques used. Furthermore, under this general behavior, results for the correction of its main errors will be extracted by means of calibration in the digital domain. Finally, two well-consolidated state-of-the-art techniques will be explained by using the developed mathematical description.
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